Power-Aware Scheduling

Dynamic Voltage and Frequency Scaling (DVFS) is the foundational hardware-software interface for power-aware scheduling. The scheduler dynamically adjusts a processor's operating voltage and clock frequency based on real-time computational workload demands.

• Mechanism: The scheduler predicts the required performance for upcoming tasks and commands the hardware to run at the lowest sufficient voltage-frequency (V-f) pair.
• Energy Savings: Since dynamic power scales with the square of the voltage (P_dyn ∝ C * V² * f), even small voltage reductions yield significant energy savings.
• TinyML Application: For bursty inference workloads, the scheduler can race-to-idle (run fast then sleep) or run at a lower, sustained frequency to minimize energy-per-inference.

This strategy schedules tasks across a mix of high-performance ("big") and ultra-efficiency ("LITTLE") CPU cores to optimize the energy-delay product (EDP).

• Task Classification: The scheduler profiles tasks (e.g., sensor data preprocessing vs. CNN layer computation) and maps them to the most energy-appropriate core.
• Migration Overhead: Efficient implementation requires minimizing the latency and energy cost of migrating tasks and cache state between cores.
• TinyML Context: Emerging microcontroller units (MCUs) feature heterogeneous clusters (e.g., Cortex-M7 + Cortex-M33). A power-aware scheduler can offload lightweight control logic to the efficiency core while reserving the performance core for intensive neural network kernels.

This technique leverages sleep states (C-states) and power gating by predicting idle periods and transitioning hardware components into low-power modes.

• State Transition Cost: Each deeper sleep state saves more power but incurs a longer, more energy-intensive wake-up latency. The scheduler must predict idle duration to select the optimal state.
• Always-On (AON) Domain: Critical wake-up logic and simple sensors remain powered in a tiny AON domain. The main processor is power-gated completely, eliminating leakage current.
• Wake-on-Event: The scheduler configures wake-on-event triggers from the AON domain (e.g., accelerometer interrupt, timer) to resume the main system only when necessary.

When operating on a finite battery or harvested energy, the scheduler must treat energy as a depletable resource to maximize operational lifetime.

• Energy Budgeting: The system allocates a daily or per-task energy budget. The scheduler prioritizes or defers tasks (e.g., model inference vs. data transmission) to stay within budget.
• Battery-Aware Mapping: Considers the battery's non-linear discharge characteristics and internal resistance, avoiding high-current draws that reduce effective capacity.
• Goal: Achieve energy-neutral operation by ensuring long-term average consumption does not exceed harvested energy, enabling perpetual sensing and inference.

This strategy co-designs the scheduler with the machine learning model architecture to exploit dynamic sparsity and conditional execution.

• Early Exit Networks: The scheduler can terminate inference at an intermediate "exit" layer for confident predictions, bypassing later, more computationally expensive layers.
• Dynamic Precision: Schedules layers or operations to run at lower numerical precision (e.g., 8-bit vs. 32-bit) when tolerable, reducing memory bandwidth and compute energy.
• Input-Dependent Scheduling: For always-on audio or vision applications, a tiny wake-word or motion detection model running on the AON domain triggers the scheduler to activate the main, more accurate model only when needed.

Dynamic Power Management (DPM) extends beyond the CPU to coordinate the power states of all system peripherals, especially sensors and radios.

• Adaptive Sampling Rate: The scheduler dynamically adjusts sensor sampling frequency based on context (e.g., lower rate for static environments), directly reducing sensor and ADC power.
• Duty Cycling: Radios are major power consumers. The scheduler aggressively duty cycles the radio, synchronizing short, high-speed bursts of data transmission with scheduled processor active periods.
• Holistic Optimization: The scheduler creates unified sleep/wake timelines for the processor, sensor, and radio, minimizing the time any major subsystem is active and avoiding wasteful state mismatches.

A foundational hardware technique that enables power-aware scheduling. DVFS dynamically adjusts a processor's operating voltage and clock frequency based on real-time computational demand.

• Core Mechanism: Lower voltage/frequency for light loads saves quadratic dynamic power (P ∝ CV²f).
• Scheduler Integration: The OS scheduler provides workload predictions, and DVFS hardware executes the voltage/frequency transitions.
• Trade-off: Aggressive downscaling saves energy but adds transition latency and can risk deadline misses if not coordinated with the task scheduler.

The algorithmic counterpart to power-aware scheduling, focusing on a fixed energy budget. This approach determines task order and timing to complete a workload before depleting a finite energy source.

• Key Difference: While power-aware scheduling minimizes energy, energy-constrained scheduling operates within a hard energy cap (e.g., a battery's remaining charge).
• Objective: Maximize system utility or completed work before energy exhaustion.
• Application: Critical for battery-operated IoT and remote sensor nodes where recharge is impossible.

A fundamental system-level power management strategy where components periodically switch between active and deep sleep states. The scheduler must align task execution with these active windows.

• Definition: Duty Cycle = (Active Time) / (Active Time + Sleep Time).
• Scheduler Role: Batch tasks to maximize contiguous active periods, minimizing the number of costly sleep-to-wake transitions.
• Example: A wireless sensor node wakes every 10 minutes for 100ms to sample, process, and transmit data, achieving a 0.017% duty cycle.

A key joint metric for evaluating scheduler efficiency, balancing performance and energy consumption. It quantifies the trade-off between saving energy and slowing down computation.

• Calculation: EDP = (Energy Consumed) × (Execution Time).
• Scheduler Goal: Find the operating point (e.g., CPU frequency) that minimizes EDP for a given workload.
• Interpretation: A lower EDP indicates a more efficient balance. A scheduler that saves energy but massively increases latency may have a worse EDP than a moderately efficient one.

The system-level policy framework within which power-aware scheduling operates. DPM makes coarse-grained decisions about component power states based on workload predictions.

• Mechanisms: Includes putting idle cores into sleep states (C-states), power-gating entire blocks, or shutting down peripherals.
• Scheduler Interaction: The task scheduler provides the activity forecasts that trigger DPM policies (e.g., "no tasks for 50ms → initiate core sleep").
• Hierarchy: DPM manages macro power states; fine-grained per-task scheduling happens within those states.

An ultra-low-power system capability that defines the trigger conditions for resuming from a sleep state. It sets the boundary conditions for scheduler inactivity.

• Mechanism: An Always-On (AON) domain with minimal power monitors a sensor or interrupt line. When a specific event occurs, it wakes the main processor.
• Scheduler Implication: The scheduler cannot run until a wake event occurs. Task deadlines must account for the potential latency from deep sleep.
• Use Case: An acoustic event detection model runs on an AON microcontroller, waking the main application processor only when a keyword is heard.