Dynamic Power Management (DPM)

Dynamic Voltage and Frequency Scaling (DVFS) is a foundational DPM technique that adjusts a processor's operating voltage and clock frequency in real-time based on computational demand. Since dynamic power consumption scales with the square of the voltage and linearly with frequency, reducing these parameters during low-activity periods yields quadratic energy savings. Modern microcontrollers integrate DVFS controllers that monitor CPU load, allowing the system to transition between high-performance and energy-saving operating points (P-states) seamlessly.

• Key Mechanism: A closed-loop controller monitors workload queues and adjusts core voltage (Vdd) and frequency (f) concurrently.
• TinyML Application: During periods of low sensor activity or between inference cycles, the MCU can down-clock its core, drastically reducing power draw while maintaining readiness.

Power gating is a circuit-level technique that uses header or footer switches to completely disconnect the power supply (Vdd or GND) to an idle hardware block. This is the most aggressive power-saving method, as it eliminates both dynamic power (from switching activity) and static power or leakage current (which becomes dominant in advanced semiconductor nodes). The trade-off is a significant wake-up latency and energy cost to restore the power domain's state.

• Fine-Grained vs. Coarse-Grained: Can be applied to individual logic gates (fine) or entire processor cores/peripherals (coarse).
• TinyML Application: Entire neural network accelerator blocks or high-speed ADCs can be power-gated when the device is in a deep sleep state, reducing standby power to nanoamps.

Clock gating is a ubiquitous power-saving technique that disables the clock signal to specific registers or logic modules when they are not in use. This eliminates the dynamic power dissipation caused by unnecessary clock toggling (which can account for 20-40% of total chip power). It is implemented at the register-transfer level (RTL) and is often automated by synthesis tools.

• Mechanism: An enable signal controls a clock-gating cell, preventing the clock from propagating to a downstream circuit block.
• TinyML Application: The clock to a digital signal processor (DSP) unit or a specific SRAM bank can be gated during phases of an inference cycle where it is not actively processing data.

Sleep states (or C-states) are predefined low-power modes where the processor halts execution and powers down non-essential circuits. Deeper states (e.g., C2, C3) turn off more components like caches and phase-locked loops, yielding lower power but higher wake-up latency. Wake-on-event is the complementary mechanism that triggers an exit from sleep based on an external signal.

• Always-On (AON) Domain: A tiny, ultra-low-power circuit section remains active to monitor wake-up triggers like timer interrupts or sensor thresholds.
• TinyML Application: A voice-activated device remains in deep sleep (microamp range) until the AON domain detects a keyword, triggering the main CPU and ML accelerator to wake up for full inference.

Power-aware scheduling is an operating system or runtime algorithm that allocates computational tasks across heterogeneous processing elements (e.g., CPU, DSP, NPU) and schedules their execution to minimize total system energy while meeting latency deadlines. It involves making decisions based on the energy-delay product (EDP) of different hardware paths.

• Key Strategies: Workload consolidation (to maximize idle time), race-to-idle (complete tasks quickly to enter low-power sleep), and exploiting hardware heterogeneity.
• TinyML Application: A scheduler might decide to run a lightweight feature extractor on a low-power DSP core and only wake the more energy-intensive NPU if a high-confidence classification is needed.

Adaptive sampling and duty cycling are sensor-focused DPM techniques. Duty cycling periodically powers the sensor and its interface circuit for a short active period (T_active) followed by a long sleep period (T_sleep). The duty cycle (T_active / (T_active + T_sleep)) directly scales average power. Adaptive sampling dynamically adjusts the sampling frequency (Fs) based on the signal's information content or event detection.

• Mechanism: An algorithm monitors signal entropy or uses a simpler, always-on analog comparator to trigger high-rate sampling only when needed.
• TinyML Application: An accelerometer-based activity monitor samples at 1Hz during sedentary periods but ramps to 100Hz upon detecting motion, saving significant sensor and ADC power.

A hardware-level power management technique that dynamically adjusts a processor's operating voltage and clock frequency in response to real-time computational load. This is a core enabler for DPM, allowing the system to match power delivery to the instantaneous performance requirement of a TinyML inference task.

• Key Mechanism: Lowering voltage reduces dynamic power consumption quadratically (P_dyn ∝ C * V² * f).
• TinyML Application: An audio wake-word detector might run the MCU at a low voltage/frequency during silent periods, then rapidly scale up to full performance when a potential trigger is detected.

A circuit design technique that uses header or footer switches to completely cut off the power supply (VDD or GND) to an idle hardware block. This eliminates both dynamic power and static leakage power, which becomes dominant in advanced semiconductor nodes.

• Contrast with Clock Gating: Clock gating only stops switching activity; power gating stops all current flow.
• Use in DPM: Within a DPM strategy, entire subsystems—like a floating-point unit or a secondary ML accelerator core—can be power-gated when the active workload does not require them.

A fundamental power-saving technique that disables the clock signal to specific registers or logic modules when they are not performing useful computation. This prevents unnecessary transistor switching, thereby eliminating the dynamic power dissipation associated with clock toggling.

• Granularity: Can be applied at fine (register-level) or coarse (module-level) granularity.
• Role in DPM: DPM policies often use clock gating as a first-step, low-latency method to save power before committing a block to a deeper, power-gated sleep state.

An ultra-low-power system architecture where a small, isolated Always-On (AON) domain remains active to monitor sensors while the main processor sleeps. A wake-on-event signal from this domain triggers the main system's reactivation via DPM.

• Typical Components: The AON domain contains a low-power comparator, a simple state machine, and a real-time clock, consuming nanowatts to microwatts.
• DPM Integration: This enables always-on sensing applications (e.g., vibration monitoring) where the high-performance ML inference engine is only woken for complex classification after a simple threshold is exceeded in the AON domain.

A fundamental power management strategy where a subsystem (e.g., a radio, sensor, or the processor itself) periodically switches between a short active state and a long low-power sleep state. The duty cycle is the ratio of active time to the total period.

• Mathematical Basis: Energy savings are proportional to the reduction in active time.
• DPM Coordination: DPM orchestrates the duty cycles of multiple independent subsystems (sensor, processor, radio) to align their active windows, minimizing the time the entire system is fully powered.

The fundamental design space in TinyML where reducing computational cost (and thus energy) often comes at the expense of model accuracy or precision. DPM operates within this trade-off.

• Techniques Involved: Using lower numerical precision (INT8 vs. FP32), employing early exit networks, or selecting a simpler model variant.
• DPM Decision: A DPM policy might select a low-accuracy, low-energy model for routine monitoring, but switch to a high-accuracy, high-energy model only when a high-confidence anomaly is detected.