Leakage Power Reduction

Power gating is the most direct method for eliminating leakage by using header switches (PMOS) or footer switches (NMOS) to completely disconnect a logic block's power supply (VDD) or ground (GND).

• Implementation: A high-Vt (high threshold voltage) sleep transistor is placed in series with the power rail.
• Trade-off: Introduces wake-up latency and requires careful design of state retention registers to preserve context during sleep.
• Use Case: Applied at the core or block level in microcontrollers to shut down non-essential peripherals or an entire CPU core between inference tasks.

MTCMOS is a design methodology that uses transistors with different threshold voltages (Vt) on the same chip to optimize the speed vs. leakage trade-off.

• High-Vt transistors are used in non-critical paths or as sleep transistors (for power gating) due to their extremely low leakage.
• Low-Vt transistors are used in critical timing paths to maintain high performance.
• Result: Creates a library of cells that allow designers to meet timing constraints with minimal leakage by strategically placing low-leakage, high-Vt cells where timing slack exists.

Body biasing dynamically adjusts a transistor's threshold voltage (Vt) by applying a voltage to its body (well) terminal, thereby modulating its leakage current.

• Reverse Body Biasing (RBB): Increases Vt to drastically reduce leakage during idle modes. Common in sleep states.
• Forward Body Biasing (FBB): Decreases Vt to boost performance (speed) when high computation is needed, at the cost of higher leakage.
• Architecture: Requires a triple-well process to independently bias NMOS and PMOS transistors. Modern techniques like Adaptive Body Biasing (ABB) adjust bias in real-time based on temperature and process variations.

Input Vector Control (IVC) is a software-driven technique that applies a specific, pre-computed input pattern to a digital block when it is idle, forcing its internal nodes into a low-leakage state.

• Mechanism: Different combinations of logic gate inputs result in different stack effects and internal node voltages, which significantly alter leakage paths. The 'best' vector minimizes the voltage difference across transistors.
• Application: Managed by firmware or a power controller before putting a core to sleep. It is a low-overhead, runtime technique that complements hardware methods.
• Limitation: Finding the optimal vector for a large block is an NP-hard problem, often solved heuristically at design time.

SCCMOS, also known as Super Cut-Off or Variable Threshold CMOS (VTCMOS), is a power gating variant that drives the gate of the sleep transistor beyond the supply rails to achieve ultra-low leakage.

• Operation: To turn the sleep transistor fully OFF, its gate is overdriven. For an NMOS footer switch, the gate is driven to a negative voltage (e.g., -0.3V). For a PMOS header, it's driven above VDD.
• Benefit: Provides an order of magnitude lower subthreshold leakage compared to standard power gating, as it pushes the transistor deeper into cutoff.
• Cost: Requires an additional charge pump or voltage generator to create the overdrive voltage, adding area and complexity.

While primarily for dynamic power, clock gating reduces leakage indirectly by preventing unnecessary switching activity, which can heat the chip and increase temperature-dependent leakage (junction temperature is a major factor in leakage current).

• Synergy with Leakage Reduction: A gated clock allows a module to be power gated more aggressively, as there is no clock toggling to manage.
• Fine-Grained vs. Coarse-Grained: Fine-grained clock gating (cell-level) stops flip-flop clocks when data is unchanged. Coarse-grained gating (module-level) enables larger blocks to be idled and is a prerequisite for applying other leakage techniques like power gating.
• Standard Practice: Implemented automatically by synthesis tools using enable signals, and is a foundational step in any low-power digital flow.

Power gating is the most direct technique for leakage power reduction. It uses header or footer MOSFET switches to completely disconnect a logic block or core from the power supply (VDD) or ground (GND). This creates a virtual power rail, eliminating all static current flow in the gated domain.

• Implementation: Requires isolation cells at the boundaries of the gated block to prevent floating signals and retention flops to save state before shutdown.
• Trade-off: Introduces a wake-up latency penalty (microseconds to milliseconds) and area overhead for the control circuitry and switches.

DVFS dynamically adjusts a processor's operating voltage and clock frequency in response to workload demands. While primarily targeting dynamic power (P_dyn ∝ C * V^2 * f), lowering VDD also exponentially reduces leakage current.

• Mechanism: Leakage current has a super-linear relationship with supply voltage. A 10% reduction in VDD can yield a >20% reduction in leakage power.
• TinyML Use: Used to run inference kernels at just-sufficient performance levels, minimizing both dynamic and static energy per inference.

MTCMOS is a foundational circuit design technique for leakage control. It uses transistors with different threshold voltages (Vth) within the same design.

• High-Vth transistors are used in non-critical paths or as sleep transistors for power gating, offering very low leakage when off.
• Low-Vth transistors are used in critical timing paths to maintain performance, accepting higher leakage.
• This creates an architectural trade-off, allowing designers to selectively gate high-leakage blocks while keeping always-on domains ultra-efficient.

NTC operates digital logic with a supply voltage (VDD) very close to the transistor's threshold voltage (Vth). This region offers the maximum energy efficiency per operation but comes with significant challenges.

• Benefit: Provides a 5-10x improvement in energy efficiency compared to standard super-threshold operation.
• Challenge: Dramatically increases circuit delay and sensitivity to process, voltage, and temperature (PVT) variations, requiring robust design and error-tolerant architectures.
• Relation to Leakage: While dynamic power drops quadratically, the sub-threshold leakage current becomes a dominant and highly variable component of total power, making its management critical.

C-States are predefined low-power modes in a processor architecture, each representing a deeper level of sleep with greater power savings and longer wake-up latency.

• C0: Active state.
• C1 (Halt): Clock gated to core.
• C2 (Stop-Clock): Clocks stopped, phase-locked loops (PLLs) on.
• C3 (Deep Sleep): Caches flushed, PLLs off, core voltage may be reduced.
• C6 (Deep Power Down): Core power-gated, state saved to dedicated SRAM.
• TinyML Context: The deepest states (C3, C6) aggressively employ clock gating, power gating, and voltage scaling to minimize leakage during long idle periods between sensor sampling or inference bursts.

An AON domain is a small, isolated power and clock domain on a system-on-chip that remains active while the main processor and most peripherals are power-gated. It is essential for wake-on-event functionality.

• Components: Typically contains a low-power real-time clock (RPC), a few general-purpose input/output pins, interrupt controllers, and a simple finite-state machine or ultra-low-power core (e.g., a Cortex-M0+).
• Function: Monitors critical sensors (e.g., accelerometer for motion detection) or a wake-up radio. Upon detecting a predefined event, it triggers the reactivation of the main power domains.
• Leakage Focus: The AON domain itself must be designed with extreme leakage reduction techniques (e.g., using only high-Vth transistors) as it is never off.