Sleep States (C-States)

A runtime power management technique that dynamically adjusts a processor's operating voltage and clock frequency in response to real-time computational demand. Lowering voltage and frequency reduces dynamic power consumption quadratically and linearly, respectively. It is often used in conjunction with C-states, which manage idle power, to optimize total energy use across active and idle periods.

A circuit-level technique that uses header or footer switches to completely cut off the power supply (VDD or GND) to an idle logic block, core, or SRAM. This eliminates both dynamic and, critically, static leakage power, which becomes dominant in deep sleep states (e.g., C6+). Power gating enables the deepest C-states but incurs a significant latency and energy cost to restore power and context.

A fundamental power-saving technique that disables the clock signal to portions of a digital circuit when they are not performing useful computation. This eliminates the dynamic power dissipation caused by unnecessary clock toggling (charging/discharging of capacitive loads). It is a primary mechanism for implementing shallow C-states (C1) and is used extensively within active cores to save power during short idle periods.

A system feature where a device in a deep sleep state (C-state) is awakened by a specific external hardware trigger, bypassing the need for periodic timer-based wake-ups. Common triggers include:

• A sensor reading exceeding a threshold
• A packet from an ultra-low-power Wake-up Radio (WuR)
• A GPIO pin transition This enables ultra-low-power always-on sensing by minimizing the duty cycle of the main processor.

A small, isolated power domain on a System-on-Chip (SoC) that remains powered and clocked while the main processor, memory, and peripherals are in a deep sleep state. The AON domain typically contains:

• Low-power real-time clocks (RTC)
• Simple state machines or microcontrollers
• Critical wake-up logic and I/O pads
• Retention memory for the main CPU's context It manages wake-up events and maintains minimal system state, enabling efficient deep C-states.

A fundamental system-level strategy where a device (e.g., radio, sensor, or main processor) periodically switches between a short active state and a long low-power sleep state. The duty cycle is the ratio of active time to the total period. For example, a 1% duty cycle radio is active for 10ms every second. This technique directly trades latency for average power savings and is the operational model that makes deep C-states valuable.