Always-On (AON) Domain

The computational heart of the AON domain is a dedicated microcontroller or processor core designed for minimal leakage current. These cores are typically:

• RISC-V or Arm Cortex-M0/M0+ class architectures.
• Optimized for sub-threshold or near-threshold voltage operation.
• Lack complex features like out-of-order execution or deep pipelines to minimize active and static power.

Their sole purpose is to execute simple control logic and sensor data preprocessing with microwatt-level power budgets.

A dedicated, power-gated memory block that remains accessible only to the AON domain. This includes:

• Small, retained SRAM (e.g., 4-64 KB) for storing state, sensor data, and wake-up code.
• Non-volatile memory (ROM/Flash) for storing the immutable AON firmware bootloader.
• Memory is isolated from the main system bus to prevent leakage paths from the powered-down main memory.

This memory is crucial for maintaining context and enabling instant resume without booting the main OS.

A hardware block that monitors digital and analog inputs for pre-programmed wake-up events without CPU intervention. It handles:

• GPIO pin state changes (e.g., button press).
• Analog comparator outputs (e.g., sensor threshold crossing).
• Timer/RTC alarms for scheduled wake-ups.
• Wake-up on pattern from low-power communication interfaces like UART or I2C.

Upon detecting a qualifying event, it triggers an interrupt to the AON processor or directly initiates the main power rail sequencing.

The AON domain is powered by a separate, always-on voltage regulator that is highly efficient at very low load currents. Key techniques include:

• Power gating isolation cells at the boundary between the AON domain and the powered-off main logic to prevent leakage.
• Level shifters for voltage translation between domains.
• Retention flip-flops that maintain state with a tiny trickle of power while the rest of a block is shut down.

This electrical isolation is fundamental to preventing the AON domain from being a parasitic load on the battery.

A set of minimal, low-power peripherals directly accessible by the AON processor for interfacing with critical sensors. This often includes:

• Low-Speed I2C/SPI controllers for environmental sensors.
• Low-power ADC for sampling analog sensors (e.g., thermistor, microphone).
• Pulse counters for simple event counting from motion or hall-effect sensors.
• Dedicated hardware accelerators for basic DSP tasks like FFT or voice activity detection to offload the AON CPU.

Data is pre-processed here to determine if a full system wake-up is justified.

The software layer that defines the AON domain's intelligence. It is a deterministic, bare-metal or RTOS-based application responsible for:

• Polling or interrupt-driven sensor management.
• Running simple TinyML models (e.g., keyword spotting, anomaly detection).
• Managing the wake-up logic and sequencing the main processor's power-up.
• Communicating with the main OS via shared memory or messaging queues upon wake-up.

This firmware is typically statically linked and stored in ROM or protected flash to ensure reliability.

Power gating is a circuit design technique that uses header or footer switches to completely cut off the power supply to an idle logic block or core. This is distinct from the AON domain, which remains powered.

• Header/Footer Switches: High-Vt transistors that act as switches in the power rail.
• Isolation Cells: Prevent floating signals from a powered-down block from causing leakage in active blocks.
• State Retention: Critical registers in a powered-down block may have a separate, always-on power supply to retain state, a concept similar to but more granular than an AON domain. The AON domain itself is a large, coarse-grained power-gated region that is never switched off.

Wake-on-event is the functional outcome enabled by the AON domain. It is a system power management feature where a deeply sleeping device is awakened by a specific external or internal trigger.

• External Triggers: GPIO pin transitions, signals from a Wake-up Radio (WuR), or interrupts from sensors connected to the AON domain.
• Internal Triggers: Timers (e.g., a Real-Time Clock in the AON domain) or a pre-processed sensor reading (e.g., "voice activity detected") from an AON-domain accelerator.
• Low-Latency Resume: The AON domain holds the system in a state where the main processor and its power rails can be restored quickly, minimizing the performance penalty of deep sleep.

Energy harvesting integration designs systems to capture ambient energy (light, vibration, RF) to power devices. The AON domain is critical for making such systems viable.

• Perpetual Operation Goal: Aims for energy-neutral operation, where long-term consumption ≤ energy harvested.
• Ultra-Low Power Basal Rate: The power budget of the AON domain (often in the 10s of µW range) is a key determinant of whether a harvester (e.g., a small solar cell) can sustain always-on sensing.
• Duty Cycling Orchestrator: The AON domain's microcontroller can manage the complex duty cycling of the main system, radio, and sensors based on available harvested energy, only waking the main processor when sufficient energy is stored.

Leakage power reduction techniques minimize the static current that flows through transistors even when they are off. The design of the AON domain is dominated by leakage considerations.

• Multi-Threshold CMOS (MTCMOS): Uses high-threshold voltage (HVT) transistors in the AON domain's logic to drastically reduce leakage, albeit at the cost of slower switching speed.
• Power Gating (Again): The main domain is power-gated from the AON domain's perspective, eliminating its leakage during sleep.
• Sub-threshold Operation: Some AON domain microcontrollers are designed to operate in the near-threshold or sub-threshold region, where supply voltage is close to or below the transistor threshold voltage, achieving phenomenal energy efficiency for simple control tasks at low frequencies.