Duty Cycling

The duty cycle (D) is the fraction of time a component is active within a total period (T). It is calculated as D = T_active / T_total. A 1% duty cycle means the device is active for 1 ms every 100 ms. This metric is the primary lever for energy savings, as power consumption scales linearly with D when sleep power is negligible. For example, a radio consuming 100 mA at 3.3V when active and 1 µA when asleep achieves an average current of ~3.3 mA at a 1% duty cycle, a 30x reduction.

Duty cycling exploits the disparity between two distinct power states:

• Active State: Full operational power (P_active). The device performs computation, sensing, or communication. Power is dominated by dynamic switching current.
• Sleep/Low-Power State: Minimal static power (P_sleep). Non-essential circuits are clock-gated or power-gated. Only critical functions like a real-time clock or wake-up logic remain active. The average power is P_avg = (D * P_active) + ((1-D) * P_sleep). Effective duty cycling requires P_sleep to be orders of magnitude smaller than P_active.

Duty cycling introduces a fundamental trade-off. Lowering the duty cycle saves energy but increases latency and response time. A device asleep cannot respond to events until its next scheduled wake-up. This is managed by:

• Fixed Periodic Wake-ups: Predictable latency, simple to implement.
• Wake-on-Event: Uses an always-on (AON) domain with ultra-low-power comparators to wake the main system only when a sensor threshold is breached, minimizing latency for critical events without constant polling.

This is the most common use case in IoT. Radios (e.g., BLE, LoRa, WiFi) are extreme power consumers. Duty cycling protocols define synchronized active windows:

• Low-Power Listening: Receiver wakes up briefly to check for a preamble signal.
• Scheduled Rendezvous (TSCH): Nodes align their active slots using a shared schedule. The goal is to minimize the time the high-power radio transmitter and receiver are on. A wake-up radio (WuR) is a specialized ultra-low-power receiver that listens continuously for a magic packet to trigger the main radio, enabling near-zero latency while maintaining a near-0% duty cycle for the main radio.

Sensors are duty-cycled to avoid continuous analog-to-digital conversion. The adaptive sampling rate is a key technique:

• Sample frequently (high D) during periods of interest or high activity.
• Sample infrequently (low D) during quiescent periods. For instance, an accelerometer might sample at 100 Hz when motion is detected but drop to 1 Hz during stillness. This requires an event detection circuit in the AON domain to classify the signal and trigger the sampling rate change, ensuring no events are missed.

Effective duty cycling requires coordinating multiple subsystems (sensor, processor, radio). Power-aware scheduling ensures all components are active simultaneously to complete a task before returning to sleep. Poor coordination causes cascading active periods, wasting energy. The sequence for a sensing node is often:

1. Wake up processor and sensor (from sleep).
2. Sample and process data.
3. Power up radio, transmit data, power down radio.
4. Return all components to sleep. The goal is to minimize the time any high-power component is active and to batch operations within the shortest possible active window.

A hardware-level power management technique that dynamically adjusts a processor's operating voltage and clock frequency in response to real-time computational workload. This reduces dynamic power consumption, which scales with the square of the voltage and linearly with frequency. In TinyML, DVFS can be applied during inference to match the compute intensity of different neural network layers.

A circuit design technique that uses header or footer switches to completely cut off the power supply (VDD or GND) to an idle logic block, core, or memory bank. This eliminates both dynamic power and static leakage power, offering the deepest power savings. It is often used in conjunction with duty cycling to power down entire subsystems during long sleep periods, but incurs a significant latency and energy cost to restore power and state.

A fundamental power-saving technique that disables the clock signal to portions of a digital circuit when they are not performing useful computation. This eliminates the dynamic power dissipation caused by unnecessary clock toggling (charging and discharging of capacitive loads). It is a finer-grained, lower-latency technique than power gating and is ubiquitously employed in processor design and neural network accelerators to gate clocks to idle arithmetic logic units (ALUs) or memory arrays.

A critical system feature that enables duty cycling by allowing a device in a deep sleep state to be awakened by a specific, low-power external trigger. This trigger is monitored by an Always-On (AON) Domain. Common triggers include:

• A sensor reading exceeding a predefined threshold.
• A specific pattern from a Wake-up Radio (WuR).
• A timer expiration (for periodic duty cycling). This mechanism is essential for creating responsive, ultra-low-power sensing applications.

A small, isolated, and ultra-low-power section of a System-on-Chip (SoC) that remains powered and active even when the main processor, memory, and other subsystems are in a deep sleep or power-gated state. Its responsibilities include:

• Monitoring simple sensors or Wake-on-Event triggers.
• Maintaining a real-time clock (RTC).
• Managing the wake-up sequence for the main processor. The AON domain is the "watchdog" that makes intelligent, scheduled duty cycling possible.

A design goal and operational paradigm for systems powered by energy harvesting (e.g., solar, thermal, RF). The system is designed so its long-term average energy consumption is less than or equal to the average energy harvested from the environment. Duty cycling is the primary knob to achieve this balance. The system must dynamically adjust its active duty cycle based on available energy to enable theoretically perpetual operation without a battery.