Polyphase Arbitrary Resampler

The core efficiency of the resampler comes from polyphase decomposition. Instead of computing a full FIR filter for every output sample and then discarding the majority of results during decimation, the prototype low-pass filter is split into M polyphase sub-filters (where M is the interpolation factor). For each output sample, only the single sub-filter aligned with the desired fractional delay is computed. This reduces the required multiply-accumulate operations (MACs) by a factor of M, making high-fidelity, real-time resampling feasible on FPGAs and ASICs.

To achieve a continuously variable resampling ratio, the polyphase resampler often employs a Farrow structure. This architecture approximates the continuous-time impulse response using piecewise polynomials.

• Mechanism: A bank of fixed FIR sub-filters computes polynomial coefficients.
• Interpolation: A fractional delay parameter, µ, is fed into a polynomial evaluator (e.g., Horner's method) to calculate the exact sample value between available polyphase branches.
• Benefit: This eliminates the need to store an infinite number of polyphase sub-filters, enabling smooth, on-the-fly adjustment of the sample rate for applications like symbol timing recovery.

The resampler intrinsically performs anti-aliasing (during decimation) and anti-imaging (during interpolation) using a single, unified low-pass filter. The prototype filter's design is critical:

• Stopband Attenuation: Must suppress spectral images and aliases below the target Spurious-Free Dynamic Range (SFDR).
• Passband Ripple: Must be minimal to avoid distorting the signal of interest.
• Transition Band: The width dictates the computational complexity; a narrower transition band requires a longer prototype filter, increasing the number of polyphase branches and the required MACs per second.

Deploying a polyphase arbitrary resampler on an FPGA requires careful fixed-point quantization. The bit-widths for filter coefficients, state variables, and the fractional delay parameter µ must be optimized to balance hardware resource consumption against numerical precision.

• Coefficient Quantization: Coarse quantization can distort the filter's frequency response, degrading stopband attenuation.
• Internal Word Growth: Accumulators must be sized to prevent overflow during the sum-of-products computation.
• Interface: The core typically uses an AXI4-Stream interface for high-throughput, deterministic data transfer, often paired with a ping-pong buffer to manage the irregular output sample rate.

A practical architectural challenge is the clock domain crossing (CDC) between the input and output sample rates. The resampler acts as a bridge between two asynchronous clock domains.

• FIFO Buffering: An asynchronous FIFO is used to safely pass data across the boundary, with its fill level managed by the resampling control logic.
• Deterministic Latency: For multi-channel, phase-coherent systems (e.g., beamforming), the total group delay through the polyphase filter must be fixed and known. The architecture must guarantee that the latency from input to output is a constant number of output clock cycles, independent of the resampling ratio, which is achieved by aligning the polyphase branch selection with a consistent timing reference.

In a wideband digital receiver, the polyphase arbitrary resampler rarely operates in isolation. It is typically the final, fine-tuning stage following a coarse decimation chain.

• Coarse Decimation: A CIC filter and subsequent FIR decimators reduce the multi-GSPS rate from the ADC to a lower, manageable rate.
• Fine Resampling: The polyphase resampler then converts this intermediate rate to the exact sample rate required by the downstream baseband processing algorithm, correcting for any non-integer decimation factors and clock mismatches between the ADC and the digital logic. This two-stage approach optimizes overall computational efficiency.

In direct RF sampling architectures, the ADC operates at a fixed high sample rate. A polyphase arbitrary resampler converts this fixed rate to the specific baseband symbol rate required by the target waveform. This allows a single hardware front-end to support GSM, LTE, 5G NR, and proprietary waveforms without changing the master clock. The resampler handles non-integer ratio conversions between the ADC clock and the waveform's fundamental sample rate, preserving phase coherency for modulation accuracy.

When paired with a polyphase filter bank, the arbitrary resampler enables independent rate adjustment for each channelized sub-band. After a wideband signal is decomposed into narrowband channels, each channel may require a different output rate for downstream processing. The resampler corrects for fractional decimation ratios that arise when the FFT size does not perfectly divide the input sample rate, ensuring each channel is presented at its optimal processing rate.

Modern arbitrary waveform generators use polyphase resamplers to synthesize signals at precise output frequencies. The technique enables fine frequency resolution by interpolating between stored waveform samples using a continuously variable delay. This is critical for generating phase-continuous frequency sweeps and simulating Doppler-shifted signals for radar and electronic warfare testing, where the output sample clock is fixed but the signal's instantaneous frequency must vary smoothly.

In digital receivers, the ADC samples asynchronously to the transmitter's symbol clock. A polyphase arbitrary resampler, driven by a timing error detector like a Gardner algorithm, interpolates the asynchronous samples to produce samples at the exact maximum eye-opening instants. This closed-loop system continuously adjusts the resampling ratio to track clock drift between the transmitter and receiver, eliminating the need for a voltage-controlled oscillator in all-digital modems.

Implementing a polyphase arbitrary resampler on an FPGA leverages the architecture's inherent parallelism. The polyphase decomposition allows the prototype filter to operate at the lower of the input or output rate, not the intermediate high rate. Combined with fixed-point quantization and CORDIC-based NCOs for phase accumulation, the design achieves high dynamic range while minimizing DSP slice and block RAM utilization. This efficiency is critical for fitting multi-channel wideband processors into a single device.

In digital pre-distortion (DPD) systems, the feedback path observing the power amplifier output often operates at a different sample rate than the transmit path. A polyphase arbitrary resampler aligns the feedback samples in time and rate with the transmitted reference. This fractional delay compensation is essential for accurate amplifier modeling, as even sub-sample misalignment degrades the cancellation of spectral regrowth and limits the achievable adjacent channel leakage ratio.