Phase Coherency

A system design property guaranteeing a fixed, known delay between input and output across all channels. This is the foundational requirement for phase coherency.

• Sample-level alignment: Every sample across all channels experiences the exact same processing delay.
• Reset synchronization: All digital down-converters and decimation chains must start from a common reset state.
• JESD204C Subclass 1: Uses SYSREF signals to achieve deterministic latency across multiple converter devices.

Without deterministic latency, the relative phase between channels becomes an unknown variable, destroying the ability to perform spatial processing.

All receiver channels must derive their mixing signals from a single, common reference oscillator. This ensures that any phase noise or drift is correlated across channels.

• Phase noise correlation: Common phase noise cancels out in relative phase measurements between channels.
• Distribution network: Requires carefully length-matched, impedance-controlled transmission lines to each down-converter.
• Coherent sampling clock: The ADC sampling clock must also be derived from the same reference to prevent clock-domain drift.

If independent oscillators are used, their uncorrelated phase noise introduces a random, time-varying phase offset that cannot be calibrated out.

Every component in the signal path before digitization must exhibit identical phase and amplitude responses across all channels.

• Filter matching: Anti-aliasing filters must have group delay matched to within fractions of a nanosecond.
• Trace length equalization: PCB traces from the antenna connector to the ADC input must be length-matched to avoid static phase offsets.
• Temperature compensation: Matched thermal characteristics prevent differential phase drift as the system heats up.

Mismatches in the analog domain create a fixed but frequency-dependent phase error that degrades beamforming null depth and direction-finding accuracy.

All digital signal processing blocks must operate on time-aligned samples from every channel simultaneously.

• Ping-pong buffer synchronization: Dual-buffer schemes must swap buffers on the same clock edge for all channels.
• AXI4-Stream framing: Use TLAST and TUSER sideband signals to mark frame boundaries that are consistent across channels.
• Clock domain crossing discipline: All channels must cross from the sample clock domain to the processing clock domain with identical latency.

A single-cycle misalignment in the digital domain introduces a phase error proportional to the signal frequency, which can be catastrophic at higher frequencies.

Even with careful hardware design, residual mismatches require digital calibration to achieve deep phase coherency.

• Factory calibration: A known test signal is injected into all channels simultaneously to measure static phase and amplitude offsets.
• In-situ pilot tone injection: A low-level reference tone is continuously injected to track and correct thermal drift during operation.
• IQ imbalance correction: Compensates for gain and phase mismatches between the I and Q paths within each channel.

Calibration coefficients are typically stored in non-volatile memory and applied as complex multipliers in the digital processing chain.

The final stage where phase-aligned samples from all channels are combined into a single coherent data structure for downstream processing.

• Corner-turn operation: Transposes data from channel-major to sample-major order for matrix-based beamforming algorithms.
• Covariance matrix construction: Phase-coherent samples enable accurate estimation of the spatial covariance matrix for MUSIC and MVDR algorithms.
• Angle-of-arrival integrity: The relative phase between channels directly encodes the incident angle of the received wavefront.

This aggregated data stream is what enables the system to spatially filter signals, null interferers, and geolocate emitters.

A system design property guaranteeing a fixed, known delay between input and output. For phase coherency, every channel in a multi-receiver array must exhibit identical deterministic latency. A variance of even a single sample clock cycle between channels introduces a phase error that degrades beamforming accuracy and direction-finding precision. This requires careful management of FIFO depths, pipeline stages, and reset synchronization across all parallel paths.

The transfer of a signal between two asynchronous clock domains in a digital circuit. Without proper synchronization, metastability can inject non-deterministic delays that destroy phase coherency. Techniques include:

• Multi-stage flip-flop synchronizers for single-bit signals
• Asynchronous FIFOs with Gray-coded pointers for multi-bit buses
• Common reference clock distribution to minimize the number of crossings Phase-coherent systems often mandate a single, shared sample clock distributed with matched-length traces to all converters.

Errors in a high-speed analog-to-digital converter array caused by gain, offset, and timing skew mismatches between parallel sub-ADCs. These mismatches create spurious tones that corrupt the phase relationship between channels. Calibration techniques include:

• Digital background calibration using correlation of the output spectrum
• Foreground calibration with a known test tone
• Statistical blind estimation based on signal distribution assumptions Uncorrected timing skew directly translates to a frequency-dependent phase error, making it a primary obstacle to achieving wideband phase coherency.

A computationally efficient structure for implementing uniform filter banks that decomposes a prototype filter into polyphase components. In a phase-coherent channelizer, the polyphase decomposition must maintain strict phase linearity across all sub-bands. The prototype filter's group delay must be constant, and the polyphase branches must be computed with identical arithmetic precision. Any asymmetry in coefficient quantization or rounding between branches introduces inter-channel phase distortion that breaks the coherent reconstruction property.

A digital compensation technique that corrects for gain and phase mismatches between the in-phase (I) and quadrature (Q) paths of a direct-conversion receiver. The ideal 90-degree phase offset between I and Q is critical for preserving the complex signal's phase information. Imbalance sources include:

• LO quadrature error in the mixer
• Gain mismatch in baseband amplifiers
• Filter response differences between I and Q paths Blind correction algorithms estimate imbalance parameters from the signal's statistical properties, restoring the phase integrity needed for coherent processing.