Inferensys

Glossary

Time-Interleaved ADC Mismatch

Errors in a high-speed analog-to-digital converter array caused by gain, offset, and timing skew mismatches between parallel sub-ADCs, requiring digital calibration.
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DIGITAL CALIBRATION

What is Time-Interleaved ADC Mismatch?

Time-interleaved ADC mismatch refers to the gain, offset, and timing skew errors between parallel sub-ADCs that create spurious frequency components, limiting the spurious-free dynamic range (SFDR) of a high-speed digitizer.

Time-interleaved ADC mismatch is the non-uniformity in gain, offset, and timing skew across an array of parallel sub-converters sampling in a round-robin sequence to achieve a higher aggregate sample rate. These mismatches generate deterministic spurs and interleaving tones in the output spectrum that are not present in the original input signal, severely degrading the spurious-free dynamic range (SFDR) and effective number of bits (ENOB).

Digital calibration is required to suppress these artifacts by estimating and correcting the mismatch parameters. Offset mismatch is corrected by subtracting the measured DC bias of each sub-ADC. Gain mismatch is compensated by normalizing the amplitude of each channel. Timing skew, the most challenging error, is corrected using fractional delay filters or derivative-based correction circuits that realign the sampling instants, often requiring a foreground or background estimation loop.

ERROR SOURCES IN INTERLEAVED ARRAYS

Three Types of TI-ADC Mismatch

Time-interleaved ADCs achieve high sample rates by multiplexing slower sub-ADCs, but mismatches between these parallel paths introduce distortion that limits spurious-free dynamic range (SFDR). The three primary mismatch types are offset, gain, and timing skew.

01

Offset Mismatch

A fixed DC voltage difference between the baseline levels of parallel sub-ADCs. This error is independent of the input signal amplitude and creates fixed-frequency spurs in the output spectrum.

  • Cause: Transistor threshold voltage variations in comparators or residue amplifiers.
  • Spectral Signature: Tones appear at multiples of fs / M, where fs is the total sample rate and M is the number of interleaved channels.
  • Calibration: Corrected by digitally subtracting the measured offset value for each sub-ADC. A common technique involves random chopping to measure and nullify the offset in the background.
02

Gain Mismatch

A difference in the full-scale voltage range or slope of the transfer function between sub-ADCs. This error scales with the input signal amplitude.

  • Cause: Mismatches in reference voltages or capacitor ratios in the sampling network.
  • Spectral Signature: Creates spurs at ±fin + k * fs / M, where fin is the input frequency. These spurs are amplitude-modulated copies of the input signal.
  • Calibration: Mitigated by multiplying each sub-ADC's output by a correction coefficient. Foreground calibration uses a known test tone, while background methods correlate the outputs of adjacent channels.
03

Timing Skew Mismatch

A deviation in the exact sampling instant of each sub-ADC from its ideal periodic position. This is the most performance-limiting mismatch at high input frequencies.

  • Cause: Mismatched clock path lengths, buffer delays, and aperture uncertainty in the track-and-hold circuits.
  • Spectral Signature: Produces spurs at the same locations as gain mismatch (±fin + k * fs / M), but the spur magnitude increases with input frequency.
  • Calibration: The most complex to correct. Digital techniques estimate the skew by correlating the derivative of the signal with the output error, then apply a fractional delay filter (e.g., a Farrow structure) to resample the data to the correct time instant.
04

Combined Impact on SFDR

In a practical TI-ADC, all three mismatches occur simultaneously, creating a complex spurious spectrum that degrades the Spurious-Free Dynamic Range (SFDR).

  • Offset spurs are fixed in frequency and independent of the input signal.
  • Gain and timing spurs move with the input frequency, making them harder to distinguish and cancel.
  • Timing skew dominates at high Nyquist-zone inputs, often requiring foreground factory calibration or sophisticated background adaptive filters to achieve >70 dB SFDR in 4+ channel arrays.
TIME-INTERLEAVED ADC MISMATCH

Frequently Asked Questions

Clear, technical answers to the most common questions about the errors that plague high-speed time-interleaved analog-to-digital converter arrays and the digital calibration techniques used to correct them.

Time-interleaved ADC mismatch refers to the non-idealities in gain, offset, and timing skew between parallel sub-ADCs that sample a signal in a round-robin sequence to achieve a higher aggregate sample rate. In an ideal M-channel time-interleaved ADC, each sub-ADC operates at Fs/M but samples at precise intervals of 1/Fs. Mismatch errors cause the sub-ADCs to deviate from this ideal, generating spurious tones in the output spectrum that are not present in the input signal. These mismatch spurs appear at specific frequency locations determined by the input frequency and the interleaving factor, severely degrading the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SINAD). The three primary mismatch types are offset mismatch, which creates fixed spurs at multiples of Fs/M; gain mismatch, which produces amplitude-modulated spurs; and timing skew mismatch, which generates frequency-dependent phase errors that worsen at higher input frequencies.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.