Thermal Resistance Network

Two canonical network topologies serve distinct purposes in thermal modeling:

• Foster Network: A behavioral model using series RC stages that provides a mathematical fit to transient heating curves. The internal nodes have no direct physical correspondence to material layers, making it ideal for compact model extraction from measured thermal impedance data.
• Cauer Network: A physically representative model where each RC stage maps to a specific material layer (die, solder, baseplate). Capacitors are connected to ground, directly correlating electrical components to thermal resistance and thermal capacitance of the physical structure.

The choice between topologies depends on whether the application requires physical insight or computational simplicity.

Each RC stage in the network defines a thermal time constant (τ = R_th × C_th) that governs the rate of temperature change. In power amplifiers, these time constants span multiple orders of magnitude:

• Die-level constants: Microsecond to millisecond range, driven by the small thermal mass of the transistor channel.
• Package-level constants: Millisecond to second range, determined by the heat spreader and substrate materials.
• Heat sink constants: Seconds to minutes, representing the large thermal capacitance of the cooling solution.

This multi-scale behavior creates the long-term memory envelope that digital predistortion must compensate for, as the junction temperature retains a history of past signal power levels.

The terminal node of a thermal resistance network is defined by the thermal boundary condition, which represents the interface to the external cooling environment. Three primary conditions govern network behavior:

• Fixed Temperature (Dirichlet): The ambient temperature is held constant, representing ideal heat sinking.
• Convective Boundary (Robin): Heat transfer to the ambient is governed by a convection coefficient, modeling air or liquid cooling with finite efficiency.
• Adiabatic (Neumann): Zero heat flux, used for symmetry planes in finite element analysis.

In practical amplifier modeling, the boundary condition directly affects the steady-state junction temperature and the long-duration tail of the thermal impulse response.

In multi-finger transistor layouts, thermal resistance networks must account for thermal crosstalk between adjacent fingers. This is modeled by coupling individual junction networks through shared thermal resistances:

• Mutual thermal resistance (R_th,mutual) quantifies the temperature rise in one finger due to power dissipated in a neighboring finger.
• The resulting thermal gradient across the device causes non-uniform gain and phase characteristics, distorting the combined output signal.
• Network complexity scales with the square of the number of fingers, requiring careful model-order reduction for real-time predistortion applications.

This coupling is particularly significant in GaN HEMT designs where high power density creates steep lateral temperature gradients.

Thermal resistance network parameters are extracted from transient thermal response measurements using the following methodology:

• A known power step is applied to the device, and the junction temperature is monitored via a temperature-sensitive electrical parameter (TSEP), typically the forward voltage of a body diode.
• The resulting thermal impedance curve (Z_th(t)) is deconvolved into a series of exponential terms, each corresponding to an RC stage.
• Structure function analysis transforms the Foster network into a Cauer network, revealing the physical heat flow path and identifying bottlenecks such as high-resistance die attach layers.

Accurate extraction is critical for building predistortion models that correctly capture the frequency-dependent thermal memory response.

The thermal resistance network serves as the dynamic core of thermal-aware digital predistortion systems by providing real-time junction temperature estimates:

• The instantaneous power dissipation waveform is convolved with the network's thermal impulse response to compute the junction temperature trajectory.
• This temperature estimate feeds into a temperature-compensated predistorter that adjusts correction coefficients based on the thermal state.
• The network's low-pass filtering characteristic explains why thermal memory effects are concentrated at low modulation frequencies (typically below 1 MHz), allowing separation from faster electrical memory effects in the predistortion architecture.

This approach enables compensation of thermal AM-AM and AM-PM distortion without requiring direct on-die temperature sensing.

Two canonical representations for fitting or physically modeling thermal impedance. The Foster model uses a series of parallel RC stages to provide a behavioral fit to transient heating curves without direct physical correspondence. The Cauer model maps each RC stage to a specific material layer (die, attach, package), with capacitors connected to ground, directly correlating electrical components to thermal resistance and thermal capacitance.

Thermal impedance defines the dynamic relationship between power dissipation and temperature rise. It is not a single value but a frequency-dependent complex quantity. The thermal time constant dictates memory duration—the characteristic time for junction temperature to reach ~63.2% of steady-state after a step change. Multiple time constants exist in a packaged device:

• Die-level: microseconds
• Package-level: milliseconds
• Heat sink: seconds to minutes

Electro-thermal modeling couples semiconductor device physics with dynamic heat generation and dissipation equations. This co-simulation technique solves the heat equation alongside electrical transport equations to predict temperature-dependent nonlinearities. Critical for capturing:

• Self-heating effects during RF envelope peaks
• Quiescent bias shift from threshold voltage drift
• Thermal AM-AM and thermal AM-PM distortion
• Interaction between GaN trapping and thermal states

Thermal-aware predistortion incorporates real-time temperature sensing or electro-thermal models into the DPD engine to compensate for dynamically shifting amplifier nonlinearities. Implementation approaches include:

• Temperature-compensated LUTs that index coefficients by amplitude and estimated junction temperature
• Thermal-induced memory polynomials with augmented terms for low-frequency thermal lag
• Thermal convolution operations that model temperature as the convolution of power dissipation with the device's thermal impulse response

In multi-finger transistors and parallel amplifier paths, thermal crosstalk occurs when power dissipated in one finger heats adjacent fingers. This creates thermal gradients across the device, causing each finger to operate at a different bias point and exhibit distinct nonlinear characteristics. The combined output exhibits distortion that cannot be corrected by a single lumped thermal model, requiring spatially-aware compensation or thermal boundary condition optimization in package design.

Thermal runaway is a destructive positive feedback loop: increased junction temperature raises leakage current, which increases power dissipation, further raising temperature until device failure. This is particularly critical in GaN HEMT devices where high power density creates extreme thermal flux. Key mitigation strategies:

• Conservative die attach thermal resistance design
• Active temperature monitoring with power back-off
• Transient thermal response characterization to identify safe operating area boundaries