Cauer Thermal Model

Unlike the behavioral Foster model, the Cauer network directly maps each RC stage to a specific physical layer in the heat dissipation path. The series resistors represent the thermal resistance of each material (die, solder, baseplate), while the grounded capacitors represent the thermal capacitance of that same layer. This one-to-one correspondence enables engineers to extract material properties directly from measured transient thermal response curves.

The defining structural feature of the Cauer model is that all thermal capacitors are connected to thermal ground (ambient temperature reference), not in parallel with the resistors as in the Foster network. This configuration accurately reflects the physical reality that heat energy is stored within each material layer relative to the ambient environment, making the Cauer model suitable for finite element analysis validation and computational fluid dynamics co-simulation.

Each internal node in the Cauer ladder corresponds to a measurable physical interface temperature:

• Node 1: Junction temperature (Tj) at the transistor channel
• Node 2: Die attach interface temperature
• Node 3: Package case temperature (Tc)
• Node N: Heat sink baseplate temperature This accessibility allows direct correlation with thermocouple measurements and infrared thermal imaging during device characterization.

The Cauer network parameters are extracted from transient thermal impedance (Zth) measurements by applying a known power step and recording the junction temperature response. The resulting heating curve is analyzed using time-constant spectrum deconvolution to identify discrete RC stages. Each stage's time constant (τ = R × C) corresponds to the thermal time constant of a specific material layer, enabling non-destructive identification of die attach voiding or package delamination defects.

The Cauer model integrates seamlessly into compact device models (such as Angelov or ASM-HEMT) for electro-thermal co-simulation. The instantaneous power dissipation calculated by the electrical solver is injected as a current source into the Cauer network, and the resulting junction temperature is fed back to update temperature-dependent parameters:

• Threshold voltage (Vth) shift
• Transconductance (gm) degradation
• Drain resistance (Rd) increase This closed-loop simulation captures thermal AM-AM and AM-PM distortion with high fidelity.

The final stage of the Cauer ladder explicitly represents the thermal boundary condition at the package-to-ambient interface. This can be configured as:

• A fixed thermal resistance to ambient (Rth,ja) for natural convection
• A forced convection coefficient for active cooling scenarios
• A temperature-dependent boundary for liquid cooling systems This flexibility makes the Cauer model essential for GaN-on-SiC power amplifier designs where precise junction temperature prediction is critical for reliability assessment and thermal-aware predistortion algorithm development.

A canonical mathematical representation of thermal impedance using a series of parallel RC ladder stages connected in series. Unlike the Cauer model, the Foster network provides a behavioral fit to transient heating curves without direct physical correspondence to material layers. The Foster model is mathematically simpler to extract from measured thermal impedance (Zth) data, making it popular for compact circuit simulation, but its nodes do not represent actual physical temperatures within the device structure.

A measure of a material's resistance to heat flow, defining the dynamic relationship between power dissipation and the resulting temperature rise. Key characteristics:

• Units: Kelvin per Watt (K/W)
• Static (Rth): Steady-state temperature rise per unit power
• Dynamic (Zth): Time-dependent thermal response capturing capacitive effects
• Zth curve extraction is the primary input for parameterizing both Cauer and Foster thermal models from measured transient thermal response data

The characteristic time required for a device's junction temperature to reach approximately 63.2% of its steady-state value following a step change in power dissipation. In the Cauer model, each RC ladder stage has its own time constant (τ = R × C), directly corresponding to the thermal lag of a specific physical layer:

• Die: Nanoseconds to microseconds
• Die attach: Microseconds to milliseconds
• Package/heat sink: Milliseconds to seconds These distributed time constants dictate the memory duration that digital predistortion must compensate.

A co-simulation technique that couples semiconductor device physics with dynamic heat generation and dissipation equations. This approach simultaneously solves:

• Electrical domain: Transistor I-V characteristics, gain, and phase response
• Thermal domain: Cauer or Foster network representing heat flow paths
• Feedback loop: Temperature-dependent parameters (threshold voltage, mobility) update electrical behavior in real-time Essential for predicting thermal AM-AM and thermal AM-PM distortion in GaN/GaAs power amplifiers under modulated signal excitation.

A mathematical operation that models junction temperature as the convolution of the instantaneous power dissipation waveform with the device's thermal impulse response. Key aspects:

• The impulse response is derived from the Cauer or Foster network transfer function
• Captures the full thermal memory effect including long-term envelope-frequency heating
• Computationally efficient for integration into thermal-aware predistortion algorithms
• Enables real-time estimation of junction temperature without physical sensors, using only the known transmitted signal envelope and pre-characterized thermal parameters

A behavioral model structure that augments standard memory polynomials with additional terms specifically designed to capture low-frequency, long-duration thermal lag effects. Structure:

• Standard terms: Capture high-frequency electrical memory (nanosecond scale)
• Thermal augmentation terms: Operate on envelope samples spaced by thermal time constants (microsecond to millisecond scale)
• Enables a single unified model to span both electrical trapping effects and self-heating dynamics
• Particularly effective for GaN HEMT devices where thermal and trapping memory interact