Thermal Capacitance

Thermal capacitance is the product of a material's specific heat capacity, density, and volume. It quantifies the amount of heat energy required to raise the temperature of a given region by one degree Kelvin. In a power amplifier, the distributed thermal capacitance of the semiconductor die, die attach, and package substrate stores energy during RF power dissipation peaks and releases it during troughs, smoothing the junction temperature response.

Thermal capacitance combines with thermal resistance to form the RC time constants that dictate a device's transient thermal response. Each material layer in the heat dissipation path—from the transistor channel to the heat sink—contributes a distinct capacitance, creating a multi-stage thermal lag. The dominant time constant, often in the millisecond to second range, falls directly within the bandwidth of modern communication signal envelopes, causing envelope-frequency-dependent distortion.

In a Foster thermal model, thermal capacitance appears in parallel RC ladder stages that mathematically fit the transient heating curve but lack direct physical correspondence. In contrast, a Cauer thermal model connects each capacitor to thermal ground, directly mapping each RC stage to a physical material layer—such as the die, solder bump, or copper flange. The Cauer representation is preferred for finite element correlation and for extracting per-layer thermal capacitance values.

The magnitude of thermal capacitance directly determines the thermal relaxation time—the duration over which a temperature perturbation persists after the stimulus is removed. High-capacitance structures, such as thick copper heat spreaders, create long-duration memory tails that span multiple OFDM symbols. This causes thermal-induced spectral asymmetry and slow quiescent bias shift, which cannot be corrected by conventional memoryless digital predistortion.

Thermal capacitance is extracted through transient thermal response measurements. A step power dissipation is applied, and the junction temperature rise is recorded via a temperature-sensitive electrical parameter, such as the base-emitter voltage of a bipolar device or the threshold voltage of a FET. The resulting heating curve is deconvolved into its constituent RC stages using network identification by deconvolution, yielding both thermal resistance and capacitance per time-constant stage.

Gallium Nitride devices exhibit high power density concentrated in small active regions, resulting in lower local thermal capacitance and faster, more pronounced self-heating transients compared to Gallium Arsenide. To mitigate this, designers increase effective thermal capacitance through thick copper heat spreaders, diamond substrates, or microfluidic cooling. These techniques shift the dominant thermal time constant upward, reducing the overlap between thermal memory bandwidth and the modulation envelope frequency.

The dynamic relationship between power dissipation and junction temperature rise. Unlike simple thermal resistance, impedance captures the time-dependent heat flow behavior caused by distributed thermal capacitance throughout the device structure. Measured in °C/W, it defines how quickly a junction responds to changes in dissipated power and is typically characterized using transient thermal response measurements.

The characteristic time for junction temperature to reach ~63.2% of steady-state after a power step. Multiple time constants exist in real devices:

• Die-level: microseconds to milliseconds (near-junction capacitance)
• Package-level: milliseconds to seconds (die attach, substrate)
• Heat sink: seconds to minutes (bulk thermal mass) These layered constants create the memory duration that DPD must compensate.

Two canonical representations of thermal impedance:

Foster Model:

• Series RC ladder stages with parallel resistors
• Behavioral fit to transient heating curves
• No direct physical correspondence to material layers

Cauer Model:

• Ladder network with capacitors to ground
• Each stage maps to a physical material layer
• Preferred for electro-thermal co-simulation

Both models provide the transfer function for thermal convolution in predistortion.

The mathematical operation that computes junction temperature as the convolution of instantaneous power dissipation with the device's thermal impulse response. This captures the history-dependent nature of thermal memory:

T_j(t) = P_diss(t) * Z_th(t)

Where Z_th(t) is the thermal impedance impulse response. This convolution forms the basis for thermal-induced memory polynomial terms in advanced DPD models, enabling compensation for envelope-frequency heating effects.

A nonlinear phase shift that varies with the envelope history of the input signal. Temperature-dependent transistor capacitances (particularly C_gs and C_gd in FETs) cause dynamic phase rotation:

• Cold junction: lower capacitance, different phase response
• Hot junction: increased capacitance, phase lag increases

This creates thermal-induced spectral asymmetry in the output spectrum—upper and lower sidebands become imbalanced—which cannot be corrected by memoryless linearization alone.

Digital linearization that incorporates real-time temperature state into correction coefficient calculation:

• Temperature-compensated LUT: indexes coefficients by both instantaneous amplitude and estimated junction temperature
• Electro-thermal model integration: runs a simplified thermal model alongside the DPD engine
• Sensor-based: uses on-die temperature sensing diodes for direct measurement

This approach is critical for GaN/GaAs amplifiers where self-heating and trapping create complex, thermally-activated nonlinearities.