Dynamic Thermal Resistance

The fundamental measure defining the dynamic relationship between power dissipation and temperature rise in a semiconductor. Unlike static thermal resistance, thermal impedance captures the time-dependent heat flow through multiple material layers. Key characteristics:

• Expressed as Z_θ(t) with units of °C/W
• Governed by the thermal capacitance of each material layer
• Extracted from transient thermal response measurements
• Forms the basis for Foster and Cauer network models

The characteristic time required for junction temperature to reach ~63.2% of steady-state after a step change in power dissipation. Multiple time constants exist in real devices:

• Die-level constants: Microsecond to millisecond range, driven by semiconductor volume
• Package-level constants: Millisecond to second range, driven by die attach and substrate
• System-level constants: Seconds to minutes, driven by heat sink and ambient coupling

These staggered time constants create the long-term memory envelope that complicates linearization.

A co-simulation methodology that couples semiconductor device physics with dynamic heat generation and dissipation equations. This approach enables:

• Prediction of temperature-dependent I-V characteristics under modulated signals
• Extraction of dynamic thermal resistance from physical device structure
• Integration with circuit simulators for transient distortion analysis
• Validation of behavioral thermal models against measured data

Essential for understanding how self-heating modifies instantaneous amplifier nonlinearity.

An augmented behavioral model that extends standard memory polynomials with low-frequency thermal terms. This structure explicitly captures:

• Long-term envelope memory beyond electrical time constants
• Thermal AM-AM and AM-PM distortion components
• Interaction between instantaneous nonlinearity and temperature history

Implementation typically adds envelope-dependent thermal kernels with time constants matched to the device's thermal impedance profile, enabling predistorters to track slow gain and phase drift.

A mathematical operation modeling junction temperature as the convolution of instantaneous power dissipation with the device's thermal impulse response. Key aspects:

• T_j(t) = P_diss(t) ∗ h_θ(t)
• The thermal impulse response h_θ(t) is derived from the Foster or Cauer network
• Captures the full history-dependent temperature trajectory
• Computationally efficient for real-time thermal-aware predistortion

This framework directly links dynamic thermal resistance to predictable distortion patterns.

The heating of one transistor finger or amplifier path by power dissipated in adjacent elements. In multi-finger GaN/GaAs devices:

• Creates thermal gradients across the die surface
• Causes non-uniform gain and phase response per finger
• Distorts the combined output through phase misalignment
• Requires distributed thermal resistance network modeling

Mitigation strategies include symmetric layout design, thermal shunting, and per-finger predistortion with thermal coupling terms.