Thermal Memory Mitigation

A closed-loop thermal management strategy that dynamically adjusts cooling effort based on real-time junction temperature or power dissipation estimates.

• Mechanism: Uses variable-speed fans, liquid flow controllers, or thermoelectric coolers (TECs) modulated by a PID controller
• Objective: Maintain a constant junction temperature regardless of signal envelope variations, effectively breaking the electro-thermal coupling
• Implementation: Integrates temperature sensors at the die attach or package baseplate with a microcontroller that anticipates thermal spikes from baseband power predictions
• Benefit: Reduces the magnitude of thermal lag by preventing large temperature swings, simplifying the residual memory that digital predistortion must correct

The design of the DC bias feed network to present a constant, low impedance across the envelope frequency heating bandwidth, preventing dynamic bias modulation.

• Key Insight: Thermal memory causes a quiescent bias shift because the transistor's threshold voltage drifts with temperature; a stiff bias network resists this shift
• Design Technique: Use of large decoupling capacitors with low equivalent series resistance (ESR) and careful placement of bias chokes to minimize low-frequency memory
• Target: Eliminate the interaction between the thermal time constant and the bias circuit's electrical time constant, which otherwise creates a compound memory effect
• Result: Reduces thermal AM-AM distortion by clamping the operating point even as device transconductance changes with temperature

An algorithmic technique that separates the slow thermal distortion component from the fast electrical nonlinearity within the digital predistortion learning architecture.

• Process: The predistorter model is augmented with a parallel thermal convolution path that estimates junction temperature from the signal envelope history
• Model Structure: Uses a thermal-induced memory polynomial where long-delay taps specifically capture the thermal relaxation time while short taps handle electrical memory
• Adaptation: The coefficient estimation algorithm jointly extracts electrical and thermal parameters by decorrelating the fast and slow distortion components
• Advantage: Prevents the DPD from attempting to correct thermal effects with inappropriate wideband coefficients, which would cause thermal-induced spectral asymmetry

A look-up table adaptation scheme where predistortion coefficients are indexed by both instantaneous signal amplitude and a measured or estimated device temperature.

• Structure: A 2D LUT with amplitude on one axis and a thermal resistance network-derived temperature estimate on the other
• Update Mechanism: The table is partitioned into temperature bins; only the active bin corresponding to the current junction temperature is updated during online training
• Sensing: Uses an on-die temperature diode or a Foster thermal model running in real-time on the FPGA to provide the temperature index
• Application: Critical for GaN trapping mitigation where the charge capture time constant is itself temperature-dependent, requiring a multi-dimensional correction surface

A multi-input predistortion technique that accounts for the heating of one amplifier path by adjacent paths in multi-finger or MIMO transmitter arrays.

• Problem: In a massive MIMO DPD system, the power dissipated by one transmit chain raises the temperature of neighboring chains via thermal crosstalk
• Modeling: Extends the electro-thermal modeling framework to include a thermal resistance network with coupling terms between adjacent transistor fingers
• Correction: The predistorter for each path receives not only its own envelope but also the delayed power envelopes of adjacent paths as inputs
• Outcome: Eliminates the spatially-dependent thermal AM-PM distortion that varies across the array, restoring beam pattern integrity

A signal conditioning technique that high-pass filters the baseband envelope to remove the low-frequency components that fall within the thermal bandwidth of the device.

• Principle: Envelope frequency heating occurs because the signal envelope contains spectral content below the thermal time constant's cutoff frequency
• Implementation: A digital filter in the transmit path attenuates envelope variations slower than the thermal cutoff, reducing the peak-to-average ratio of the temperature waveform
• Trade-off: Slightly increases peak-to-average power ratio of the RF signal but dramatically reduces the magnitude of thermal lag
• Synergy: Combined with thermal-aware predistortion, this reduces the dynamic range over which the thermal model must operate, improving numerical stability

A digital linearization technique that incorporates real-time temperature sensing or electro-thermal models into the predistorter. Unlike conventional DPD that assumes a static PA characteristic, thermal-aware DPD dynamically adjusts correction coefficients based on estimated or measured junction temperature. This compensates for the shifting AM-AM and AM-PM curves caused by self-heating. Implementation typically involves:

• Augmenting the predistorter input vector with a temperature state variable
• Using a temperature-compensated LUT with 2D indexing (amplitude + temperature)
• Embedding a real-time thermal convolution model to estimate junction temperature from power dissipation history

Circuit-level technique to minimize quiescent bias shift caused by temperature fluctuations. The bias network supplies the DC operating point for the transistor, and its thermal stability directly impacts distortion. Key strategies include:

• Active bias compensation using temperature-sensing diodes and feedback loops
• Selecting bias resistors with low temperature coefficient of resistance (TCR)
• Implementing constant-current biasing rather than constant-voltage to stabilize drain current over temperature
• Using current mirrors with thermal tracking to maintain consistent quiescent conditions across multi-finger devices

Dynamic thermal management that modulates cooling effort in response to real-time power dissipation. Rather than relying on passive heat sinks alone, active systems reduce the amplitude of junction temperature swings that cause thermal memory. Approaches include:

• Variable-speed fan control keyed to transmit power levels or duty cycle
• Liquid cooling with proportional valve actuation for high-power base station amplifiers
• Thermoelectric coolers (TECs) for precision temperature stabilization in sensitive GaN/GaAs devices
• Pre-cooling during low-power transmission slots to reduce peak temperature excursions during high-power bursts

A signal processing technique that mathematically removes the thermal memory contribution from the observed PA output, isolating the faster electrical nonlinearities for separate compensation. The process involves:

• Modeling the thermal impulse response of the device using a Foster or Cauer network
• Computing the estimated thermal distortion component via thermal convolution of the input envelope
• Subtracting the thermal contribution from the measured output before extracting the electrical DPD coefficients
• This decoupling allows the main predistorter to operate on a thermally 'clean' signal, improving linearization bandwidth and reducing coefficient adaptation complexity

A mitigation strategy that exploits the frequency-domain separation between electrical and thermal memory effects. Thermal time constants typically range from microseconds to milliseconds, corresponding to envelope frequencies below ~100 kHz, while electrical memory effects occupy higher bandwidths. Techniques include:

• High-pass filtering the predistorter training signal to exclude low-frequency thermal components during coefficient extraction
• Designing the DPD learning architecture with separate paths for thermal and electrical correction
• Using multi-rate processing where thermal compensation updates at a slower rate than the main DPD engine, reducing computational overhead

Fundamental semiconductor design choices that reduce thermal memory at its source. These techniques address the thermal resistance network from junction to ambient before any algorithmic compensation is applied:

• GaN-on-SiC substrates offering 3-5x higher thermal conductivity than GaN-on-Si
• Flip-chip mounting eliminating wire bonds and reducing die attach thermal resistance
• Copper-molybdenum (CuMo) carriers as CTE-matched heat spreaders
• Microfluidic cooling channels etched directly into the substrate for sub-millisecond thermal response
• Multi-finger layouts with optimized spacing to minimize thermal crosstalk between adjacent transistor fingers