Dataflow Architecture

In a dataflow architecture, computational nodes—often called actors—fire or execute the moment all required input tokens (data packets) are present at their input ports. This is fundamentally different from a von Neumann architecture, where a program counter dictates instruction order. For DPD, this means a complex multiplier actor immediately processes a new I/Q sample pair the instant it arrives from the ADC interface, eliminating idle cycles and ensuring deterministic, low-latency correction. The absence of a global clock for scheduling removes control hazards and simplifies the parallelization of the predistortion pipeline.

Dataflow architectures are inherently suited to deep pipelining, a critical optimization for high-speed DPD. A complex operation, such as a memory polynomial evaluation, is decomposed into a chain of smaller actors (e.g., magnitude calculation, LUT indexing, complex multiply, accumulate). Registers are inserted between each stage, forming a pipeline. While this increases latency by a fixed number of clock cycles, it dramatically increases the maximum clock frequency (Fmax) and allows a new sample to be accepted on every clock cycle. This enables the predistorter core to sustain the multi-gigasample per second throughputs required for wideband 5G signals.

A dataflow graph explicitly exposes both task-level and data-level parallelism. Independent actors with no data dependencies can execute concurrently without complex orchestration logic. In a multi-band DPD system, for instance, the predistortion data paths for Band 1 and Band 2 are represented as separate, parallel subgraphs. On an FPGA, these are synthesized into independent hardware blocks that operate simultaneously. This spatial parallelism is a key advantage over sequential DSP processors, allowing a single FPGA to linearize multiple transmit paths or antenna elements in a Massive MIMO array.

The dataflow model is a perfect semantic match for AXI4-Stream interfaces, the standard protocol for connecting high-speed data paths in FPGA designs. An AXI4-Stream bus uses a simple valid/ready handshake, where data is transferred only when the source is valid and the sink is ready. This directly implements the token-passing mechanism of a dataflow actor. A DPD IP core designed as a dataflow graph can be trivially wrapped with AXI4-Stream interfaces, allowing it to be seamlessly integrated into a larger system using tools like Vivado IP Integrator, connecting directly to DACs, ADCs, and other processing cores.

Modern High-Level Synthesis (HLS) tools, such as Vitis HLS, are fundamentally dataflow compilers. When a developer writes a DPD algorithm in C++, the HLS tool analyzes the data dependencies between functions and loops to construct a dataflow graph. By applying the DATAFLOW pragma, the designer instructs the tool to synthesize independent functions into concurrently executing hardware modules that communicate via ping-pong buffers or FIFOs. This allows for rapid exploration of different DPD architectures—such as comparing an ILA vs. DLA topology—by modifying C++ code rather than manually re-architecting RTL.

Unlike a cached processor where execution time is variable, a pure dataflow implementation on an FPGA has a statically analyzable, deterministic latency from input to output. The delay is simply the sum of the pipeline register stages and combinational logic delays along the critical path. This property is crucial for DPD, where the time alignment between the reference signal and the feedback observation must be known with sample-level precision. A fixed, known latency in the predistorter core simplifies the correlation and alignment algorithms required for accurate power amplifier model extraction.