DPD Feedback Path

A directional coupler at the PA output samples a small fraction of the transmitted signal. This sample is then precisely attenuated to match the linear input range of the observation receiver's analog-to-digital converter (ADC). Over-attenuation degrades signal-to-noise ratio (SNR), while under-attenuation saturates the ADC, clipping the waveform and destroying the nonlinear information critical for model extraction.

The coupled RF signal is downconverted to baseband or an intermediate frequency (IF) using a local oscillator (LO) synchronized with the transmitter. A quadrature demodulator separates the signal into in-phase (I) and quadrature (Q) components. Any mismatch in gain or phase between the I and Q branches introduces IQ imbalance, a distortion that must be compensated for independently of the PA nonlinearity to prevent the DPD model from learning a corrupted representation of the amplifier's behavior.

The baseband I/Q signals are digitized by high-speed ADCs. The feedback ADC must have sufficient effective number of bits (ENOB) and spurious-free dynamic range (SFDR) to capture the PA's nonlinear distortion products, which can extend 3-5x beyond the original signal bandwidth. For a 100 MHz 5G NR carrier with fifth-order intermodulation products, the observation receiver requires an instantaneous bandwidth of at least 500 MHz to avoid aliasing the distortion components.

The feedback signal experiences a fixed but unknown propagation delay through the coupler, cables, downconverter, and ADC pipeline. Time alignment correlates the transmitted reference waveform with the received feedback to estimate this delay with sub-sample precision using fractional delay filters. A misalignment of even a single sample can cause the DPD coefficient estimation to converge to an incorrect solution, degrading adjacent channel leakage ratio (ACLR) rather than improving it.

The observation ADC often operates at a different sample rate than the predistorter processing rate. Sample rate conversion (SRC) — typically using polyphase filter banks or Farrow structures — resamples the feedback data to match the DPD processing clock domain. This step must preserve the spectral integrity of the distortion products while managing clock domain crossing (CDC) metastability risks when bridging asynchronous ADC and FPGA fabric clocks.

The observation path itself must be significantly more linear than the PA under test. Any nonlinearity in the feedback receiver — from the LNA, mixer, or ADC buffer amplifier — becomes indistinguishable from PA distortion in the captured data. The rule of thumb: the feedback receiver's third-order intercept point (IP3) should be at least 10 dB higher than the PA's output-referred IP3 to ensure the extracted model represents the amplifier alone.

A critical signal processing step that precisely synchronizes the transmitted reference signal with the received feedback signal. Without sub-sample accuracy, the DPD model will attempt to linearize a misaligned version of the distortion, severely degrading performance. Techniques include cross-correlation with fractional delay interpolation using Farrow structures to achieve picosecond-level alignment. This step compensates for the group delay through the PA, couplers, cables, and observation receiver.

The process of changing the sampling rate of a discrete signal, often required in the DPD feedback path to align the bandwidth of the observation receiver with the predistorter's processing rate. The ADC may sample at a higher rate to capture harmonic distortion for wideband linearization, while the predistorter core operates at the baseband rate. Polyphase filter banks and Farrow interpolators are common FPGA implementations that provide arbitrary ratio conversion with minimal resource usage.

The passage of a signal between two asynchronous clock domains on an FPGA. In DPD systems, the ADC sample clock, processing clock, and DAC clock often operate at different frequencies. Improper CDC handling causes metastability, leading to corrupted feedback samples and model divergence. Mitigation techniques include dual-flop synchronizers for single-bit signals and asynchronous FIFOs with Gray-coded pointers for multi-bit data buses.

A serializer/deserializer transceiver block in an FPGA that converts parallel data into a high-speed serial stream and vice versa. Forms the physical layer for JESD204B links to data converters in the feedback path. Modern SERDES in UltraScale+ and Versal architectures support line rates exceeding 32 Gbps. The transceiver includes PLLs for clock recovery, CDR circuits, and programmable equalization to compensate for channel loss on PCB traces.