Complex Multiplier

A complex multiplication (a + jb) × (c + jd) is decomposed into four real multiplications and two additions: (ac - bd) + j(ad + bc). In DPD hardware, this is typically implemented using DSP48 slices on Xilinx FPGAs, which natively support 25×18-bit multiply-accumulate operations. The real and imaginary paths are computed in parallel to maintain throughput, with the cross-product terms requiring careful alignment to avoid pipeline stalls.

In a Look-Up Table (LUT) DPD architecture, the complex multiplier applies pre-computed correction coefficients indexed by the instantaneous input magnitude. The input signal's envelope |x(n)| is computed using a CORDIC algorithm or a magnitude estimator, then used to address a dual-port RAM containing complex gain values. The multiplier then applies this retrieved coefficient to the delayed input sample, correcting both AM-AM and AM-PM distortion in a single operation.

To meet the high clock rates required for wideband DPD (typically 245.76 MHz to 491.52 MHz for 100 MHz 5G NR carriers), the complex multiplier is heavily pipelined. Register stages are inserted after each multiplication and addition operation, breaking the critical path. A fully pipelined complex multiplier may have 6-8 cycles of latency but can sustain one complex product per clock cycle, essential for real-time sample-by-sample predistortion without backpressure.

DPD complex multipliers operate in fixed-point arithmetic to minimize FPGA resource consumption. Typical implementations use 16-bit I/Q inputs and 16-bit complex coefficients, producing 32-bit products that are then truncated or rounded to 16 bits. The quantization noise introduced by this truncation must be carefully modeled—insufficient bit width degrades Error Vector Magnitude (EVM) and Adjacent Channel Leakage Ratio (ACLR) performance, while excessive width wastes DSP resources.

The complex multiplier is typically wrapped in an AXI4-Stream interface for seamless integration into the FPGA dataflow. The input TDATA bus carries interleaved I/Q samples, with TVALID and TREADY signals managing flow control. This standardized interface allows the multiplier to be dropped into a Vivado IP Integrator block design, connecting directly to the predistorter's coefficient memory, the CFR output, and the DAC interface without custom glue logic.

On a Xilinx RFSoC device, a single 16×16-bit complex multiplier consumes approximately 3 DSP48E2 slices when using the dedicated pre-adder for cross-term optimization. For a DPD system processing a 100 MHz carrier at 245.76 MSPS, the complex multiplier in the forward path represents less than 1% of the total DSP resources on a ZU28DR device, leaving ample headroom for the CFR engine, model extraction logic, and additional carrier processing.