Knee Voltage

Knee voltage is the minimum drain-to-source voltage (V_DS) at which a FET enters the saturation region, where the drain current becomes essentially independent of V_DS. Below this voltage, the transistor operates in the linear or triode region, behaving as a voltage-controlled resistor. Above V_k, the channel is pinched off near the drain, and further increases in V_DS produce only marginal increases in drain current. This transition point is critical because the maximum linear output voltage swing of a power amplifier is bounded by the supply voltage minus the knee voltage.

A lower knee voltage directly translates to higher power-added efficiency (PAE) and drain efficiency. The knee voltage represents a minimum voltage headroom that must be maintained across the transistor to keep it in saturation. Any voltage dropped below V_k during the RF cycle results in the transistor entering the lossy ohmic region, dissipating power as heat rather than delivering it to the load. For a given supply voltage V_DD, the theoretical maximum drain efficiency is proportional to:

• (V_DD - V_k) / V_DD for Class-A operation
• Approaching 100% for ideal switch-mode operation as V_k → 0

In Doherty amplifier designs, the knee voltage of both the carrier and peaking devices sets the fundamental limit on achievable back-off efficiency.

Knee voltage is fundamentally determined by the semiconductor material properties and device geometry:

• GaN HEMTs: Exhibit exceptionally low knee voltages (typically 2-5V) due to high electron mobility, high sheet carrier density, and wide bandgap enabling higher operating voltages. This is a primary reason GaN dominates modern high-efficiency Doherty designs.
• GaAs pHEMTs: Moderate knee voltages (typically 0.5-2V) with excellent high-frequency performance, though limited by lower breakdown voltages.
• LDMOS: Higher knee voltages (typically 3-8V) due to lower electron mobility in silicon, though continuously improving with advanced process nodes.

The on-resistance (R_ON) of the transistor directly scales the knee voltage: V_k ≈ I_DSS × R_ON, where I_DSS is the saturated drain current.

The knee voltage imposes a hard constraint on the maximum output power (P_OUT) that a power amplifier can deliver to a given load impedance R_L. The maximum linear output power is:

P_OUT,max = (V_DD - V_k)² / (2 × R_L)

This relationship reveals that reducing V_k from 5V to 2V in a 28V supply system increases achievable output power by approximately 25% for the same load impedance. In Doherty amplifier design, the knee voltage of the peaking amplifier directly affects the maximum power at saturation, while the carrier amplifier's knee voltage influences the back-off efficiency profile. Designers must account for V_k when selecting the optimal load impedance through load-pull analysis.

The shape of the I-V curve transition at the knee point significantly impacts linearizability by digital predistortion (DPD):

• Hard Knee: An abrupt, sharp transition from the ohmic to saturation region, typical of ideal MOSFET models. Creates strong nonlinearity near compression that is challenging for polynomial-based DPD models to correct.
• Soft Knee: A gradual, smooth transition characteristic of GaN HEMT devices, where gain compression occurs progressively. This gentler nonlinearity is more amenable to linearization by memory polynomial and neural network DPD architectures.

The soft knee behavior of GaN devices is advantageous because it produces less spectral regrowth for a given amount of gain compression, easing the burden on the DPD system to meet ACLR specifications.

Knee voltage is experimentally extracted from pulsed I-V measurements to avoid self-heating effects that distort the DC characteristics. The extraction methodology involves:

• Pulsed I-V characterization: Applying short-duration pulses (typically < 1 µs) with low duty cycle to capture the isothermal device response.
• Constant current method: Defining V_k as the V_DS at which the drain current reaches a specified percentage (e.g., 95% or 98%) of the fully saturated current I_DSS at a given gate bias.
• Load-pull verification: Confirming the extracted knee voltage through large-signal load-pull measurements under realistic modulated signal drive conditions.

Accurate V_k extraction is essential for constructing behavioral models such as the Angelov or Curtice models used in harmonic balance simulations of Doherty amplifier designs.

The operating region of a field-effect transistor (FET) where the drain current remains relatively constant regardless of increases in drain-to-source voltage. A device enters saturation when the drain voltage exceeds the pinch-off voltage, which is directly related to the knee voltage. In this region, the transistor behaves as a voltage-controlled current source, providing the gain necessary for amplifier operation. The transition point between the linear (ohmic) region and saturation is marked by the knee voltage, making it a critical parameter for determining the minimum drain voltage required for proper Class-AB and Class-C biasing in Doherty architectures.

The finite drain-to-source resistance of a FET when operating in the linear (ohmic) region below the knee voltage. A lower Rds-on directly correlates with a lower knee voltage, as the device transitions to saturation at a smaller drain voltage. This parameter is dominated by channel doping, gate length, and electron mobility in technologies like GaN HEMTs and LDMOS. Minimizing Rds-on is essential for reducing I²R conduction losses in switching-mode power amplifiers and for maximizing the voltage swing available for RF output in linear amplifier classes.

The ratio of RF output power to DC input power delivered to the drain of a power amplifier, expressed as a percentage. Drain efficiency is fundamentally limited by the knee voltage because the minimum instantaneous drain voltage during the RF cycle cannot swing below Vknee without entering the lossy linear region. A lower knee voltage enables a larger voltage swing for a given DC supply, directly increasing the theoretical maximum efficiency. In Doherty amplifiers, GaN transistors with low knee voltage are preferred precisely because they maximize drain efficiency at back-off power levels.

The gate-to-source voltage at which the conductive channel in a FET is fully depleted, reducing drain current to essentially zero. While distinct from knee voltage, the pinch-off voltage establishes the threshold conditions for channel formation. The knee voltage is the drain voltage required to pinch off the channel at the drain end, creating the saturation condition. In GaN HEMT devices, the relationship between pinch-off and knee voltage is influenced by the two-dimensional electron gas (2DEG) density and the gate-to-drain spacing, making it a key design parameter for low-voltage operation.

A graphical analysis technique that plots the instantaneous drain current versus drain voltage trajectory over a complete RF cycle on the transistor's I-V characteristic curves. The optimal load line for maximum power and efficiency extends from the DC supply voltage down to the knee voltage at peak current. A high knee voltage compresses the available voltage swing, forcing the load line into a higher impedance and reducing output power. Doherty amplifier designers use load-pull analysis to determine the optimal load impedance that positions the load line to just graze the knee voltage boundary without entering compression.

A comparative analysis of knee voltage characteristics between competing RF power transistor technologies. GaN HEMTs typically exhibit knee voltages in the range of 3-5V for a 48V supply, while LDMOS devices may show higher knee voltages of 5-10V due to their lower electron mobility and higher on-resistance. This difference gives GaN a decisive advantage in power-added efficiency (PAE) and output power density. However, GaN's sharper knee transition can introduce soft compression characteristics that require more sophisticated digital predistortion models to linearize effectively.