Harmonic Termination

Class-F operation uses harmonic resonators to shape waveforms toward ideal square-wave (voltage) and half-sine (current) shapes, minimizing overlap and theoretically achieving 100% drain efficiency.

• Second harmonic: Short-circuit termination forces voltage to zero at 2f₀
• Third harmonic: Open-circuit termination flattens voltage waveform at 3f₀
• Odd harmonics: Present an open circuit to square the voltage
• Even harmonics: Present a short circuit to shape the current

Practical implementations typically control only the 2nd and 3rd harmonics due to diminishing returns and matching network complexity at higher orders.

Inverse Class-F (Class-F⁻¹) reverses the termination scheme: open circuit at the second harmonic and short circuit at the third harmonic. This produces a half-sinusoidal voltage waveform and a square-wave current waveform.

• Advantage: Lower peak voltage stress on the transistor for the same output power
• Benefit: Particularly suited for GaN HEMT devices with low knee voltage
• Trade-off: Higher peak current requires robust current-handling capability
• Efficiency: Matches Class-F theoretical maximum of 100%

The choice between Class-F and Inverse Class-F often depends on the specific transistor technology and its voltage versus current handling limitations.

Continuous Class-B/J and Class-F modes expand the single-point optimum impedance to a continuous impedance space on the Smith chart, maintaining efficiency across a range of reactive harmonic terminations.

• Class-J: Second harmonic termination varies from short to open with appropriate fundamental reactance
• Benefit: Significantly broadens bandwidth compared to fixed harmonic shorts/opens
• Mechanism: Reactive harmonic terminations introduce phase shifts that reshape waveforms while preserving the zero-voltage, zero-current switching condition
• Application: Critical for wideband Doherty amplifiers where fixed harmonic traps limit bandwidth

This theory demonstrates that efficiency is maintained not at a single impedance point but along a continuous design trajectory.

Harmonic load-pull is the systematic measurement technique used to characterize the optimal harmonic impedances for a specific transistor under large-signal drive conditions.

• Fundamental load-pull: Varies Γ_L at f₀ to map power and efficiency contours
• Harmonic load-pull: Actively controls Γ_L at 2f₀, 3f₀, and sometimes 4f₀
• Active tuning: Uses injected signals to synthesize reflection coefficients > 1 at harmonic frequencies
• Output: Identifies the optimum harmonic impedance constellation for maximum PAE

This data directly informs the synthesis of output matching networks that present the correct harmonic terminations at the transistor's intrinsic current source plane, not just at the package reference plane.

A critical challenge in harmonic termination design is presenting the intended impedance at the intrinsic current source of the transistor die, not at the external package leads or connector.

• Parasitic network: Transistor package parasitics (bond wires, lead frames) rotate impedances significantly at harmonic frequencies
• De-embedding: Uses S-parameter models of the package and transistor parasitics to mathematically translate reference planes
• Cds and Lout: The drain-source capacitance and output inductance form a low-pass filter that attenuates harmonic voltages at the external terminal
• Design implication: The external matching network must pre-compensate for these parasitics to achieve the correct intrinsic harmonic termination

Failure to account for this plane shift results in suboptimal waveform shaping and degraded efficiency despite apparently correct external terminations.

In Doherty architectures, harmonic termination interacts with the load modulation mechanism, requiring careful co-design of the combiner network to maintain proper harmonic control across the dynamic impedance range.

• Carrier path: Harmonic terminations must remain effective as the load impedance varies from high-efficiency back-off to saturation
• Peaking path: Harmonic terminations engage only when the peaking amplifier activates at high power
• Combiner interaction: The impedance inverter at f₀ does not necessarily provide the correct transformation at 2f₀ or 3f₀
• Solution: Post-matching topologies place harmonic control networks before the Doherty combiner, isolating harmonic shaping from load modulation effects

This co-design challenge is central to achieving high-efficiency Doherty operation across the full dynamic power range.