Inferensys

Glossary

ARM TrustZone

ARM TrustZone is a system-wide hardware security technology integrated into ARM processors that creates an isolated 'secure world' to execute trusted applications and protect sensitive data from the 'normal world' operating system.
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SECURE ENCLAVE EXECUTION

What is ARM TrustZone?

ARM TrustZone is a hardware-enforced security architecture for creating isolated execution environments on ARM-based systems-on-chip (SoCs).

ARM TrustZone is a system-wide security technology integrated into ARM Cortex-A and Cortex-M series processors. It creates two parallel execution worlds—the Normal World for the rich operating system (e.g., Linux, Android) and the Secure World for trusted applications—using hardware isolation at the CPU core level. This partitioning is managed by a secure monitor layer, which controls context switching between worlds, ensuring the Secure World's code and data are inaccessible from the Normal World, even by a compromised kernel or hypervisor.

The technology establishes a hardware root of trust and a minimal Trusted Computing Base (TCB) for the Secure World. It is commonly used to protect cryptographic keys, biometric data, payment credentials, and Digital Rights Management (DRM) operations. For AI systems, TrustZone can isolate sensitive tool-calling logic or model weights, providing a Trusted Execution Environment (TEE) for secure agent operations on mobile and edge devices. It forms the foundation for other security features like Trusted Firmware and supports Remote Attestation to verify the integrity of the secure environment.

SECURE ENCLAVE EXECUTION

Core Architectural Principles

ARM TrustZone is a hardware-based security extension for ARM processors that creates two isolated execution worlds—a Secure World for trusted code and a Normal World for the general-purpose OS—enabling a root of trust for sensitive operations.

01

Dual-World Architecture

The core of TrustZone is its dual-world (or dual-core) architecture, which partitions the system-on-chip (SoC) into two execution states: the Normal World (Non-secure state) and the Secure World (Secure state).

  • Hardware Isolation: The separation is enforced at the bus fabric level. Every memory and peripheral access is tagged with a security attribute (NS bit).
  • Secure Monitor: A firmware component, the Secure Monitor, acts as a gatekeeper, managing context switches between the two worlds via a dedicated instruction (SMC - Secure Monitor Call).
  • Minimal TCB: The Secure World hosts a small, verified Trusted Execution Environment (TEE) OS (like OP-TEE), drastically reducing the attack surface compared to the full Normal World OS.
02

Hardware-Enforced Isolation

TrustZone's security is not software-based; it is hardware-mandated. The isolation extends across the entire SoC, creating a system-wide security perimeter.

  • Memory Protection: The TrustZone Address Space Controller (TZASC) partitions DRAM into secure and non-secure regions. The TrustZone Memory Adapter (TZMA) partitions on-chip SRAM.
  • Peripheral Protection: The TrustZone Protection Controller (TZPC) configures system peripherals (e.g., crypto accelerators, key storage) as secure or non-secure, preventing Normal World access.
  • Cache Tagging: Caches are tagged with the world identifier, preventing secure data from leaking into non-secure cache lines.
03

Trusted Applications & Use Cases

Within the Secure World, Trusted Applications (TAs) execute in isolation. These are small, security-critical functions accessed by Normal World applications via a controlled API.

  • Digital Rights Management (DRM): Decrypting premium media content (e.g., Widevine L1).
  • Mobile Payments: Securing fingerprint data and transaction authorization for services like Google Pay and Samsung Pay.
  • Device Rooting Prevention: Protecting the secure boot chain and verifying OS integrity.
  • Enterprise Security: Isolated corporate data containers and biometric authentication vaults.
04

Attestation & Secure Boot

TrustZone establishes a hardware root of trust that enables verified boot and remote attestation.

  • Secure Boot: The immutable boot ROM (in the Secure World) cryptographically verifies each subsequent bootloader stage before execution, creating a chain of trust.
  • Remote Attestation: The Secure World can generate a cryptographically signed report (attestation token) that proves the device's identity and the integrity of the Secure World's software to a remote server. This is critical for provisioning credentials and accessing enterprise services.
05

Comparison with Other TEEs

TrustZone is one implementation of a Trusted Execution Environment (TEE). Key distinctions:

  • vs. Intel SGX: SGX creates enclaves (isolated memory regions) within the Normal World OS process. TrustZone creates a separate world orthogonal to the OS. SGX is application-focused; TrustZone is system-focused.
  • vs. AMD SEV: SEV encrypts entire Virtual Machine (VM) memory for cloud servers. TrustZone is designed for single-system isolation on embedded and mobile SoCs.
  • vs. Software Sandboxes: Solutions like eBPF or Seccomp are software-enforced isolation within the OS kernel. TrustZone provides hardware-enforced isolation from the kernel.
06

Security Considerations & Attacks

While robust, TrustZone is not impervious. Its security depends on correct implementation and is subject to specific threat models.

  • Side-Channel Attacks: Vulnerabilities like Cache Timing Attacks can potentially leak information across worlds if the hardware design is flawed.
  • Secure World Malware: A compromised Trusted Application or TEE OS can undermine the entire system, as it operates at the highest privilege level.
  • Fault Injection: Physical attacks like glitching can attempt to bypass hardware security checks.
  • Reduced Attack Surface: The primary defense is the minimal Trusted Computing Base (TCB) of the Secure World, making formal verification of its components a critical best practice.
SECURE ENCLAVE EXECUTION

How ARM TrustZone Works: The Two-World Model

ARM TrustZone is a hardware-enforced security architecture that partitions a system-on-chip (SoC) into two isolated execution domains: a **Normal World** for the rich operating system and a **Secure World** for trusted applications.

The core mechanism is a single, dedicated secure monitor bit within the processor. This bit acts as a hardware switch, toggling the CPU's entire view of memory and peripherals between the two worlds. Code in the Normal World cannot access Secure World resources, creating a fundamental hardware barrier. This isolation extends beyond the CPU to system buses, memory controllers, and peripherals, which can be designated as secure or non-secure.

Software transitions between worlds occur via a dedicated Secure Monitor Call (SMC) instruction or hardware interrupts, which trap execution to the secure monitor firmware. This firmware, part of the Trusted Computing Base (TCB), validates the context switch. Within the Secure World, a minimal Trusted Execution Environment (TEE) OS, such as OP-TEE, manages trusted applications that handle sensitive operations like key storage, secure boot, and payment authentication, shielded from the compromised Normal World.

ARM TRUSTZONE

Frequently Asked Questions

ARM TrustZone is a foundational hardware security technology for system-on-chip (SoC) designs. These questions address its architecture, applications, and role in securing AI agent execution.

ARM TrustZone is a system-wide hardware security technology integrated into ARM processors that creates two parallel, isolated execution worlds: a Normal World for the rich operating system (e.g., Linux, Android) and a Secure World for trusted applications and sensitive data. It works by extending the concept of privilege rings (EL0-EL3 in ARMv8) with a dedicated hardware signal, the Non-Secure (NS) bit, attached to every bus transaction. This bit tags all memory, cache, and peripheral accesses, allowing the hardware to strictly partition resources. The Secure Monitor firmware, running at the highest privilege level (EL3), manages context switches between the two worlds via a dedicated instruction (SMC - Secure Monitor Call). This hardware-enforced isolation ensures code and data in the Secure World are protected from compromise in the Normal World, even if the OS kernel is fully compromised.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.