Power Side-Channel

Correlation Power Analysis (CPA) is an enhanced form of DPA that uses the Pearson correlation coefficient as its statistical distinguisher. It is often more efficient, requiring fewer power traces to succeed compared to classical DPA.

• Mechanism: Similar to DPA, CPA uses a power model (like Hamming weight or distance). It computes the correlation coefficient between the modeled power consumption for all key guesses and the actual measured power consumption at each sample point across all traces. The key guess that produces the highest absolute correlation value is the correct one.
• Advantage over DPA: The correlation coefficient provides a more sensitive measure of linear relationship, making it better at identifying the correct key with a smaller set of traces, especially when using accurate power models.
• Tooling: This is the attack most commonly implemented in open-source side-channel analysis toolkits like ChipWhisperer.

Template Attacks are considered the most powerful form of power analysis in a profiled setting. They involve a two-phase process: building a precise multivariate model (template) of a device's power consumption in a controlled environment, and then using this model to attack a target device.

• Phase 1 - Profiling: The attacker uses a fully controlled, identical device to capture many power traces for known data and keys. For each possible value of a sensitive intermediate (e.g., an S-box output), they build a multivariate probability distribution (template) characterizing the mean and covariance of the power consumption.
• Phase 2 - Attack: On the target device, a single or few power traces are captured. The attacker computes the probability that the trace was generated by each template. The template with the highest probability reveals the secret intermediate value and thus the key.
• Application: Highly effective against implementations with strong DPA/CPA countermeasures, as it models the actual, complex leakage of the specific device.

Mutual Information Analysis (MIA) is a non-parametric attack that uses information-theoretic metrics, rather than linear correlation, to discern the correct key. It is effective when the relationship between the data and power consumption is non-linear.

• Mechanism: MIA measures the Mutual Information between the hypothetical power consumption (modeled from a key guess) and the actual measured power traces. Mutual information quantifies how much knowing one variable reduces uncertainty about the other.
• Advantage: Unlike CPA, it does not assume a specific linear power model (e.g., Hamming weight). It can capture any statistical dependency, making it robust against devices with complex, non-linear leakage functions that might defeat correlation-based attacks.
• Drawback: Typically requires more traces to converge to a successful result compared to CPA when the leakage is linear.

High-Order Power Analysis targets implementations protected by masking schemes. While first-order masking randomizes intermediate values to break the correlation in a single point in time, high-order attacks combine leakage from multiple points in time (or multiple spatial locations) to defeat the masking.

• Concept: A masking scheme splits a secret value s into d+1 shares (e.g., s = m ⊕ r), where m is the masked value and r is a random mask. A first-order attack looks at the leakage of m or r alone, which is independent of s. A d-th order attack statistically combines the leakage from d shares (e.g., the power consumption when m and r are processed) to reconstruct information about s.
• Mechanism: Uses statistical moments (like variance, product) or other combining functions across multiple sample points in a single trace. For example, a second-order DPA might compute the product of the power traces at two specific times before performing correlation.
• Defense: Requires higher-order masking (increasing d), which incurs significant performance and area overhead, making it a key trade-off in secure circuit design.

A runtime power management technique that dynamically adjusts a processor's operating voltage and clock frequency based on real-time computational workload. Lowering voltage and frequency reduces dynamic power consumption quadratically and linearly, respectively. This is critical for TinyML to match compute capability to the demands of an inference task, avoiding wasted energy from an over-provisioned processor.

A circuit-level technique that uses header or footer switches to completely cut off the power supply (VDD or GND) to an idle logic block, core, or SRAM bank. This eliminates both dynamic power and static leakage power in the gated region. In TinyML systems, power gating is applied to non-essential peripherals or unused neural network accelerator blocks between inference bursts to achieve nanoampere-level sleep currents.

A fundamental power-saving technique that disables the clock signal to portions of a digital circuit when they are not performing useful computation. This prevents unnecessary transistor toggling, eliminating the dynamic power dissipation associated with charging and discharging capacitive loads. In a TinyML accelerator, clock gating is applied at fine granularity (e.g., to unused multiplier arrays) during inference execution.

A small, isolated, and ultra-low-power section of a system-on-chip (SoC) that remains powered and clocked while the main processor and other subsystems are in a deep sleep state. The AON domain typically contains:

• A simple, low-power processor (e.g., a Cortex-M0+).
• Critical wake-up logic and timers.
• A minimal set of always-on sensors or sensor interfaces. Its role is to monitor for wake-up events, enabling wake-on-event functionality for battery-powered TinyML sensors.

The foundational technique for managing energy in wireless and sensing systems. It involves periodically switching a subsystem (e.g., radio, sensor, or full processor) between a short, high-power active state and a long, low-power sleep state. The duty cycle is the ratio of active time to the total period. For example, a 1% duty cycle means the device is active for 10ms every second. This is the primary method for achieving multi-year battery life in intermittent TinyML applications.

The key performance-per-watt metric for evaluating the energy efficiency of machine learning hardware and software. It measures the number of neural network inferences a system can perform per joule of energy consumed (inferences/joule). This metric directly benchmarks the trade-offs made by model compression, quantization, and hardware acceleration in TinyML. It is the ultimate figure of merit for battery-constrained edge AI deployments.