Advanced Configuration and Power Interface (ACPI)

ACPI Machine Language (AML) is a platform-independent, interpreted bytecode language stored within ACPI tables (primarily the DSDT and SSDTs). It encodes the hardware-specific control methods for power management, thermal control, and device configuration. The operating system loads an AML interpreter (part of the ACPI driver) to execute these methods. This abstraction allows a single OS driver to manage diverse hardware without needing custom drivers for every chipset. AML is compiled from a higher-level language called ACPI Source Language (ASL).

Global System States (G-States) define the overall power state of the entire system, ranging from full operation to mechanical off.

• G0 (S0) - Working: The system is fully operational. This is the normal working state.
• G1 - Sleeping: The system appears off but retains enough context (in memory) to return to G0 quickly. This includes the S1, S2, S3, and S4 sleep states.
• G2 (S5) - Soft Off: The system is off but some components remain powered so it can be turned on via an external event (e.g., keyboard, LAN). Main system context is lost.
• G3 - Mechanical Off: The system is completely disconnected from power; no electrical current is flowing. Returning to G0 requires a full boot.

Sleeping States (S-States) are a subset of the G1 state, defining increasingly deeper levels of system sleep with correspondingly longer wake-up latencies.

• S1: A low-latency sleep where the CPU caches are flushed and the CPU(s) stop executing instructions. Power is maintained to CPU and RAM.
• S2: A deeper state than S1; the CPU is powered off. Rarely implemented.
• S3 (Suspend-to-RAM): The most common sleep state. System context is saved to DRAM, which remains powered. Nearly all other components are powered down. Provides a good balance of power savings and resume speed.
• S4 (Suspend-to-Disk / Hibernation): All system context is saved to non-volatile storage (e.g., disk). The system is effectively off (power can be removed). Resume involves restoring the saved image from disk.

Device Power States (D-States) define the power state of individual devices, independent of the global system state. This allows the OS to power down unused peripherals even when the system is in G0.

• D0 (Fully On): The device is fully operational.
• D1, D2: Intermediate device-specific low-power states. Definitions and power savings vary by device class.
• D3 (Off): The device is powered off. D3hot means the device is physically connected to power and can assert a wake signal. D3cold means the device is completely disconnected from power rails.

These states manage CPU power and performance within the G0/S0 working state. Processor Performance States (P-States): These are active operational states defined by varying the CPU's voltage and frequency (via Dynamic Voltage and Frequency Scaling - DVFS). P0 is the highest performance state; P1, P2, etc., are lower-performance, more efficient states. Processor Idle States (C-States): These are idle states entered when the CPU core has no instructions to execute (HLT instruction). Deeper C-states (C1, C2, C3) turn off more internal CPU components (caches, clock) to save power, but have higher entry/exit latency. C0 is the active state.

A runtime power management technique that dynamically adjusts a processor's operating voltage and clock frequency based on real-time computational demand. In TinyML, DVFS is critical for matching a microcontroller's power draw to the intensity of the inference task, saving energy during periods of low activity.

• Core Mechanism: Lowering voltage reduces dynamic power quadratically (P_dyn ∝ C * V^2 * f).
• TinyML Application: Used to throttle the CPU or ML accelerator during lightweight sensor processing, then ramp up for complex model layers.
• Trade-off: Aggressive down-scaling increases inference latency, requiring careful scheduling.

A circuit-level technique that uses header or footer switches to completely cut off the power supply (VDD or GND) to an idle hardware block, eliminating both dynamic power and static leakage power.

• Implementation: Applied to entire processor cores, SRAM banks, or peripheral blocks when not in use.
• TinyML Context: Essential for deep sleep states between inference intervals on battery-powered sensors. The always-on (AON) domain remains powered to monitor for wake-up events.
• Cost: Introduces state retention overhead and a latency penalty for powering the block back on.

A fundamental power-saving technique that disables the clock signal to portions of a digital circuit when they are not performing useful computation. This eliminates the dynamic power dissipation caused by unnecessary clock toggling.

• Granularity: Can be applied at the module, register, or even gate level.
• TinyML Benefit: Used extensively within ML accelerator cores to freeze unused arithmetic logic units (ALUs) and data paths during inference.
• Contrast with Power Gating: Saves only dynamic power; leakage current persists as the circuit remains powered.

The key performance-per-watt metric for evaluating the energy efficiency of machine learning hardware. It measures the number of neural network inferences a system can perform per joule of energy consumed.

• Calculation: Inferences per Watt = (Throughput in inferences/sec) / (Average Power in Watts).
• TinyML Benchmark: The primary figure of merit for comparing microcontroller inference engines (e.g., Arm Ethos-U55 vs. custom accelerators).
• Design Driver: Optimizing this metric directly extends battery life in deployed edge AI products.

A system power management feature where a device in a deep sleep state is awakened by a specific, low-power external trigger. This enables ultra-low-power always-on sensing without requiring the main processor to be active.

• Triggers: Can be a sensor interrupt (e.g., accelerometer exceeding threshold), a GPIO pin change, or a packet from a wake-up radio.
• TinyML Use Case: A microphone's analog front-end or a PIR motion sensor remains active in the AON domain, waking the main core only when a potential sound or motion event is detected for full ML inference.

The fundamental design space in TinyML where reducing computational cost saves energy but may decrease model prediction accuracy. System architects navigate this trade-off to meet application-specific requirements.

• Techniques Involved: Post-training quantization (8-bit vs. 4-bit), weight pruning, early exit networks, and adaptive sampling rates.
• Engineering Decision: For a vibration-based predictive maintenance sensor, a 5% drop in anomaly detection F1-score might be acceptable to triple the battery life from 1 to 3 years.
• Metric: Often evaluated using Pareto curves plotting accuracy against energy per inference.