Inferensys

Glossary

Polyphase Filtering

An efficient implementation of decimation and interpolation that rearranges filter coefficients into parallel sub-filters, enabling operations at the lower output sample rate to significantly reduce computational load.
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MULTIRATE SIGNAL PROCESSING

What is Polyphase Filtering?

A computational optimization technique for sample rate conversion that restructures a finite impulse response (FIR) filter into parallel sub-filters operating at a reduced clock rate.

Polyphase filtering is an efficient implementation structure for decimation and interpolation that decomposes a prototype FIR filter into P parallel sub-filters, known as polyphase branches. By rearranging the filter coefficients and leveraging the noble identities of multirate signal processing, the filtering operation is performed at the lower output sample rate rather than the high input rate, dramatically reducing the required multiply-accumulate operations (MACs) per second.

In a decimator, the input samples are commutated across the polyphase branches, and the sub-filter outputs are summed to produce the downsampled result. For interpolation, the input samples are distributed to the branches, filtered, and then interleaved at the higher rate. This architecture is foundational in modern digital down converters (DDCs), software-defined radio channelizers, and any system requiring efficient sample rate conversion without wasting compute cycles on samples destined for discard.

Computational Efficiency

Key Characteristics of Polyphase Filters

Polyphase decomposition is a fundamental signal processing technique that restructures finite impulse response (FIR) filters to perform decimation and interpolation with maximum computational efficiency.

01

Noble Identity Exploitation

The core principle enabling polyphase efficiency is the Noble Identity, which mathematically proves that filtering followed by downsampling is equivalent to downsampling followed by filtering with a decomposed filter. This identity allows the filter to operate at the lower output sample rate rather than the high input rate.

  • Reduces multiply-accumulate operations by a factor equal to the decimation ratio
  • Eliminates the computation of samples that would be immediately discarded
  • Applies identically to interpolation through the transposed Noble Identity
02

Coefficient Decomposition Structure

A prototype FIR filter of length N is decomposed into M parallel sub-filters, where M is the resampling factor. Each sub-filter contains coefficients selected from the original filter at intervals of M, starting at a different phase offset.

  • Sub-filter 0: coefficients h[0], h[M], h[2M], ...
  • Sub-filter 1: coefficients h[1], h[M+1], h[2M+1], ...
  • Each sub-filter operates at 1/M the original sample rate
  • The structure is inherently parallel and suitable for hardware implementation
03

Decimator Architecture

In a polyphase decimator, the input signal is commutated across M sub-filters in a counter-clockwise rotation. The commutator delivers each input sample to the next sub-filter in sequence, and the outputs of all sub-filters are summed to produce the decimated output.

  • Input commutator rotates at the high sample rate
  • Each sub-filter processes only every M-th sample
  • Output is produced at the decimated rate fs/M
  • Eliminates the need for a separate downsampling stage
04

Interpolator Architecture

The polyphase interpolator reverses the decimator structure. The input signal is broadcast to all M sub-filters simultaneously, and an output commutator rotates to select the output of each sub-filter in sequence, inserting M-1 computed samples between each original input.

  • Input is distributed to all sub-filters at the low sample rate
  • Output commutator rotates at the high sample rate M*fs
  • Each sub-filter computes a different fractional delay
  • Zero-stuffing and subsequent filtering are combined into one efficient operation
05

Fractional Rate Conversion

Polyphase filters enable arbitrary rational resampling ratios L/M by cascading an interpolator (factor L) with a decimator (factor M). The intermediate filter operates at L times the input rate, but polyphase decomposition ensures only non-zero samples are processed.

  • Supports ratios like 3/2, 5/4, or 147/160
  • The interpolation and decimation filters can share a single prototype
  • Critical for symbol timing recovery in software-defined radios
  • Enables sample rate alignment between asynchronous digital domains
06

Computational Savings Quantified

For a decimation-by-M filter with N taps, a direct implementation requires N multiplications per input sample. The polyphase implementation requires only N/M multiplications per input sample, a reduction factor of M.

  • Example: N=128, M=8 → 128 vs 16 multiplications per input sample
  • 87.5% reduction in multiply-accumulate operations
  • Power savings directly proportional for hardware implementations
  • Enables real-time wideband processing on resource-constrained FPGAs and DSPs
POLYPHASE FILTERING

Frequently Asked Questions

Clear, technically precise answers to the most common questions about polyphase filter banks, their computational advantages, and their role in modern digital signal processing systems.

Polyphase filtering is a computationally efficient implementation of multirate digital signal processing that restructures a finite impulse response (FIR) filter into a set of parallel sub-filters operating at a lower sample rate. The core mechanism involves decomposing the original filter's impulse response into M polyphase components, where M is the decimation or interpolation factor. For a decimation-by-M system, the input signal is first commutated across these M sub-filters, and their outputs are summed to produce the filtered, downsampled result. This rearrangement exploits the noble identities of multirate signal processing, which allow the downsampling operation to be moved before the filtering stage. Consequently, the multiply-accumulate (MAC) operations are performed at the lower output rate rather than the high input rate, reducing the computational load by a factor of approximately M. The technique is foundational in software-defined radio (SDR) digital down converters (DDCs) and channelizers.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.