CORDIC Algorithm

CORDIC replaces complex multiplications with simple binary shifts and additions. At each iteration, the algorithm rotates a vector by a predetermined elementary angle stored in a lookup table. The rotation direction is determined by the sign of the remaining angle, converging toward the target through successive approximations. This eliminates the need for hardware multipliers, reducing silicon area and power consumption in FPGA and ASIC implementations.

CORDIC operates in two fundamental modes:

• Rotation Mode: Rotates an input vector by a specified angle, computing sine and cosine simultaneously. The angle accumulator is driven to zero.
• Vectoring Mode: Determines the magnitude and phase angle of an input vector by rotating it to align with the x-axis. The y-component is driven to zero. Both modes use the same core hardware, enabling a single CORDIC engine to compute multiple transcendental functions.

CORDIC is the foundational engine for direct digital synthesis (DDS) in software-defined radios. By operating in rotation mode with a linearly incrementing phase accumulator, CORDIC generates high-resolution, frequency-agile sine and cosine waveforms. This enables precise digital down-conversion (DDC) and carrier generation without analog phase-locked loops, achieving sub-hertz frequency resolution and instantaneous phase-continuous frequency hopping.

Hardware designers choose between two CORDIC architectures based on throughput and area constraints:

• Iterative (Folded): A single CORDIC stage is reused across multiple clock cycles. Minimal logic resources but lower throughput.
• Pipelined (Unrolled): Each iteration is a dedicated hardware stage, enabling one output per clock cycle after initial latency. Ideal for high-speed digital down-conversion chains in modern direct-RF sampling receivers. The trade-off is silicon area versus sample rate.

Beyond circular trigonometric functions, the unified CORDIC formulation extends to hyperbolic and linear coordinate systems by modifying the elementary angle sequence. This generalization enables computation of:

• Hyperbolic functions: sinh, cosh, tanh, and their inverses
• Exponential and natural logarithm: via hyperbolic identities
• Square root and division: via linear mode operations A single CORDIC processor can thus serve as a universal math accelerator for digital signal processing pipelines.

Each CORDIC microrotation introduces a constant scale factor gain due to the non-unitary rotation matrix. For circular mode, the cumulative gain converges to approximately 1.64676. Compensation strategies include:

• Post-scaling: Multiply the final output by the reciprocal constant.
• Pre-scaling: Apply the inverse factor to the initial input vector.
• Double-iteration techniques: Modify the algorithm to maintain unity gain, eliminating the need for separate scaling multipliers at the cost of additional iterations.

A digital signal generator that creates a synchronous, discrete-time, discrete-valued representation of a waveform, usually sinusoidal. The CORDIC algorithm is the classic hardware-efficient engine for the NCO's phase-to-amplitude converter, iteratively rotating a vector by a phase accumulator value to generate high-spurious-free dynamic range (SFDR) sine and cosine outputs without lookup tables. This is the foundational block for Digital Down Conversion (DDC).

A rotation in a plane used to zero out specific elements in a matrix. The CORDIC algorithm operates in rotation mode to perform these transformations. It is a critical operation in QR decomposition for adaptive beamforming and MIMO channel matrix inversion, where a series of CORDIC-based Givens rotations decompose a matrix into an orthogonal matrix Q and an upper triangular matrix R without costly square-root operations.

Determining the envelope of a complex IQ signal, defined as sqrt(I² + Q²). The CORDIC algorithm in vectoring mode computes this magnitude by rotating the input vector to the x-axis, where the x-component directly represents the magnitude. This provides an efficient, multiplier-free method for Automatic Gain Control (AGC) loops and envelope detection in polar transmitters.

The CORDIC algorithm maps exceptionally well to hardware logic fabrics due to its reliance on only shifts and adds. A fully pipelined CORDIC core can produce a new output every clock cycle at very high throughput, while a serial architecture reuses a single adder stage to minimize area. This makes it a staple in Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) for software-defined radio modems.