A Time-Interleaved ADC is an architecture that uses an array of M identical sub-ADCs, each sampling the input signal at a rate of Fs/M, with their sampling clocks precisely offset by a phase of 2π/M. This round-robin operation multiplies the system's aggregate sample rate to Fs, enabling digitization speeds far beyond the capability of a single converter on the same silicon process.
Glossary
Time-Interleaved ADC

What is Time-Interleaved ADC?
A time-interleaved ADC is a high-speed analog-to-digital converter architecture that achieves a multiplied aggregate sample rate by operating multiple slower sub-ADCs in a parallel, time-staggered sequence.
The primary challenge of this architecture is interleaving mismatch: static gain, offset, and timing skew errors between the parallel sub-ADCs. These mismatches produce deterministic, periodic spurs in the output spectrum that are not present in the input signal. For RF fingerprinting, these mismatch spurs are a dominant, highly exploitable hardware signature, as they are unique to each physical chip and extremely difficult to calibrate perfectly.
Key Characteristics of TI-ADC Fingerprints
The unique fingerprint of a Time-Interleaved ADC arises from deterministic mismatches between its parallel sub-ADC channels. These static errors produce periodic, predictable spurs in the output spectrum that are highly distinct and exploitable for hardware authentication.
Gain Mismatch Spurs
Variations in the full-scale amplitude range between sub-ADCs create amplitude-modulated artifacts in the digitized output. A gain error in one channel scales its samples relative to others, producing spurs at frequencies of f_in ± k * (f_s / M), where M is the number of interleaved channels and k is an integer.
- Signature: Spurs appear as amplitude modulation sidebands around the input signal.
- Exploitability: Gain mismatch is static over short timeframes, making it a stable, high-confidence identifying feature.
- Measurement: Quantified as the percentage deviation from the mean gain across all channels.
Offset Mismatch Tones
Each sub-ADC possesses a unique DC offset voltage. When channels are cycled, this creates a fixed, periodic pattern of DC shifts at the interleaving rate. This produces a distinct set of spurs in the frequency domain that are completely independent of the input signal.
- Signature: Fixed tones at multiples of the channel switching rate (k * f_s / M).
- Key Feature: These tones persist even with no input signal present, acting as a constant, always-on beacon for device identification.
- Origin: Caused by random transistor threshold voltage mismatches in each sub-ADC's front-end comparator.
Timing Skew Error
The most critical mismatch is the deterministic clock phase error between channels. Instead of sampling at exact intervals of T_s, one channel consistently samples slightly early or late. This non-uniform sampling phase-modulates the input signal.
- Signature: Spurs appear at the same locations as gain mismatch but with a 90-degree phase shift relative to the signal, making them orthogonal.
- Impact: Timing skew errors grow linearly with input frequency, dominating the error budget in wideband systems.
- Fingerprint Value: Extremely sensitive to physical layout parasitics, making it a highly unique, process-dependent signature.
Bandwidth Mismatch
Differences in the input sampling network bandwidth of each sub-ADC channel cause frequency-dependent gain and phase errors. The track-and-hold circuit in each channel has a slightly different RC time constant due to on-resistance and capacitance variations.
- Signature: The effective gain and phase error for a channel become a function of the input frequency, not just a static value.
- Complexity: This introduces a dynamic, frequency-dependent fingerprint that is significantly harder to clone or calibrate out.
- Modeling: Requires a per-channel transfer function H_i(jω) rather than a simple scalar gain error.
Periodic Non-Stationarity
The composite output of a TI-ADC is a cyclostationary process. Its statistical properties—specifically the variance of the error—are not constant but vary periodically with the channel switching sequence. This is a fundamental departure from a standard ADC's stationary noise behavior.
- Analysis: This periodicity is directly observable in the autocorrelation function of the output error signal.
- Fingerprint Extraction: Cyclostationary analysis techniques can isolate the periodic error power from the random thermal noise floor, enhancing the signal-to-noise ratio of the fingerprint.
- Distinction: A perfectly matched TI-ADC would produce a stationary error; the degree of non-stationarity is a direct measure of the mismatch signature strength.
Interleaving Aliasing Artifacts
Mismatch errors cause aliasing of out-of-band noise and distortion back into the Nyquist band. The periodic switching of offset and gain errors effectively multiplies the input signal by a periodic sequence, convolving the signal spectrum with the mismatch spectrum.
- Mechanism: Broadband noise from each channel is folded back into the first Nyquist zone at multiples of f_s/M.
- Result: The in-band noise floor is not flat but exhibits a channel-dependent noise pedestal with periodic peaks.
- Exploitation: The specific shape of this folded noise spectrum is a direct map of the per-channel noise power spectral density, creating a rich, multi-dimensional fingerprint.
Frequently Asked Questions
Explore the core concepts behind time-interleaved analog-to-digital converters and how their inherent mismatches create exploitable hardware fingerprints for physical-layer device authentication.
A time-interleaved ADC (TI-ADC) is an architecture that achieves a higher aggregate sample rate by operating multiple, slower sub-ADCs in a parallel, round-robin sequence. Each of the M sub-converters samples the input signal at a phase offset of 2π/M, with the final digital output multiplexed to reconstruct a waveform sampled at M times the individual sub-ADC rate. The fundamental trade-off is that the aggregate Nyquist bandwidth is multiplied by M without requiring any single converter to operate at the full speed, but the performance is critically dependent on the precise matching of gain, offset, and sampling clock timing between the parallel channels. Any deviation from ideal interleaving introduces deterministic, periodic errors that manifest as distinct spurious frequency components in the output spectrum, which are the primary source of the device's unique hardware fingerprint.
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Related Terms
Understanding time-interleaved ADC architectures requires familiarity with the specific mismatch errors and performance metrics that define their unique hardware fingerprints.
Interleaving Mismatch
The static gain, offset, and timing skew errors between parallel sub-converters in a time-interleaved ADC. These mismatches produce deterministic, repetitive spurs in the output spectrum at frequencies of f_s/M and its multiples, where M is the number of interleaved channels. This is the dominant and most exploitable hardware signature in TI-ADCs.
- Gain mismatch: Amplitude modulation of the sampled signal by channel-dependent scaling factors
- Offset mismatch: A fixed DC pattern that repeats every M samples, creating tones at multiples of f_s/M independent of the input
- Timing skew: Channel-dependent sampling clock phase errors that produce input-frequency-dependent spurs
Timing Skew Calibration
A class of digital and analog techniques used to detect and correct sampling clock phase errors between interleaved channels. Without calibration, picosecond-level skews create spurs that severely degrade SFDR. Foreground methods inject a known test tone, while background techniques estimate skew from the digitized signal itself using statistical correlation.
- Foreground calibration: High accuracy but requires interrupting normal operation
- Background calibration: Runs continuously by exploiting signal statistics or injecting low-level pilot tones
- Derivative-based estimation: Uses the product of adjacent channel outputs to estimate relative timing error
Gain Error
The deviation of the actual slope of a data converter's transfer function from the ideal slope. In a time-interleaved ADC, channel-to-channel gain mismatch scales each sub-ADC's output differently, creating amplitude modulation sidebands around the mismatch spur frequencies. This static linear imperfection contributes a systematic, identifiable bias.
- Expressed as a percentage of full-scale range or in LSBs
- Interacts with offset error to create a composite DC and low-frequency signature
- Can be calibrated digitally by multiplying each channel's output by a correction coefficient
Offset Error
A constant, static voltage difference between the ideal and actual transfer function of a data converter. In a TI-ADC, each sub-converter has its own DC offset, creating a fixed pattern that repeats every M samples. This pattern produces tones at multiples of f_s/M that are completely independent of the input signal.
- Creates a deterministic, input-independent fingerprint
- Offset tones are the easiest mismatch spurs to identify and exploit
- Typically calibrated by measuring and subtracting the mean output of each channel in the digital domain
Spurious-Free Dynamic Range (SFDR)
The ratio of the fundamental signal's RMS amplitude to the highest spurious component in the output spectrum. In time-interleaved ADCs, interleaving mismatch spurs are often the SFDR-limiting factor, making this metric a direct indicator of the strength of a device's exploitable fingerprint.
- Measured in dBc (relative to carrier) or dBFS (relative to full scale)
- A TI-ADC with poor calibration may exhibit SFDR limited to 40-50 dB by mismatch spurs
- Post-calibration SFDR improvements of 20-30 dB are typical in high-performance designs
Clock Jitter
The short-term, non-cumulative deviation of a clock edge from its ideal position in time. In a TI-ADC, the shared sampling clock's aperture jitter directly translates to sampling uncertainty, while channel-specific clock skew creates the interleaving timing mismatch. Both contribute phase noise and broadband noise pedestals.
- Random jitter: Gaussian-distributed timing errors that raise the noise floor
- Deterministic jitter: Periodic timing variations from coupling or power supply, creating identifiable spurs
- Jitter requirements scale with input frequency: a 1 ps RMS jitter limits SNR to ~50 dB at 1 GHz input

About the author
Prasad Kumkar
CEO & MD, Inference Systems
Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.
His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.
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