Interleaving Mismatch

When parallel sub-ADCs in a time-interleaved array have differing voltage gains, the output amplitude modulates at the sub-ADC rotation rate. This produces deterministic spurs located at frequencies of f_s/M ± f_in, where M is the number of interleaved channels and f_in is the input frequency. The amplitude of these spurs is directly proportional to the gain error percentage, creating a static, repeatable spectral signature that is independent of the input signal's modulation scheme.

Each sub-ADC possesses a unique DC offset voltage. When the converters are cycled in a round-robin sequence, this creates a periodic fixed-pattern noise at the channel switching rate. The resulting spurs appear at integer multiples of f_s/M and are completely independent of the input signal. These tones are exceptionally stable over time and temperature, making them a highly reliable component of the device's physical-layer fingerprint for emitter identification.

Clock path mismatches cause each sub-ADC to sample at a slightly different instant, introducing a phase modulation on the digitized output. This timing skew produces spurs at the same frequencies as gain mismatch but with a 90-degree phase shift relative to the gain error components. The spur amplitude increases linearly with input frequency, making this signature dominant at higher signal bandwidths and a critical feature for distinguishing high-performance converters.

The mismatch errors create a cyclostationary noise profile where the statistical properties of the error vary periodically with the sub-ADC rotation. This means the error is not white noise but a deterministic, time-varying bias that repeats every M samples. Advanced fingerprinting algorithms exploit this periodic structure using cyclostationary feature extraction to isolate the interleaving signature from random thermal noise and channel effects.

Modern high-speed ADCs employ on-chip calibration to suppress interleaving spurs, but perfect cancellation is physically impossible. The residual mismatch after calibration—often at the -70 to -90 dBc level—remains a unique, manufacturer-specific artifact. These residuals are shaped by the calibration algorithm's finite precision and the process-voltage-temperature (PVT) conditions at the moment of factory trimming, creating a persistent, unclonable signature.

While interleaving mismatch is static at a fixed operating point, the gain, offset, and timing errors drift slowly with temperature gradients across the die and component aging. This drift follows a predictable, device-specific trajectory that can be modeled with polynomial compensation. Tracking this trajectory over time provides a multi-dimensional fingerprint that is far more difficult to spoof than a single static measurement.

An architecture that uses M parallel sub-ADCs sampling in a round-robin sequence to achieve an aggregate sample rate M times higher than a single converter. The fundamental trade-off is that any mismatch in gain, offset, or sampling clock phase between the sub-ADCs generates deterministic spurs that are not present in a single-channel design. These spurs appear at frequencies determined by the input frequency, the sampling rate, and the number of interleaved channels, creating a periodic, hardware-specific spectral pattern.

The deviation of the actual slope of a data converter's transfer function from the ideal slope. In a time-interleaved system, gain mismatch between sub-ADCs causes amplitude modulation of the digitized signal at a rate of Fs/M, where Fs is the aggregate sample rate and M is the number of channels. This produces a deterministic spur at Fs/M ± Fin in the output spectrum. The magnitude of this spur is directly proportional to the gain difference and the input signal amplitude, making it a stable, measurable component of the device fingerprint.

A constant, static voltage difference between the ideal and actual transfer function of a data converter. In a time-interleaved ADC, offset mismatch between sub-ADCs introduces a fixed DC bias that alternates with each channel in the sampling sequence. This produces a fixed-amplitude spur at integer multiples of Fs/M in the output spectrum, independent of the input signal. Because this spur is signal-independent, it is one of the most easily identifiable and persistent components of a device's interleaving fingerprint.

The static deviation of a sub-ADC's sampling instant from its ideal, uniformly spaced position in the interleaved sequence. Timing skew causes a phase modulation of the sampled signal, producing a spur at the same frequency as gain mismatch (Fs/M ± Fin) but with an amplitude that increases linearly with input frequency. This frequency-dependent behavior is a key distinguishing feature: at high input frequencies, timing skew often dominates the mismatch signature, while at low frequencies, gain and offset errors are more prominent.

The ratio of the fundamental signal's RMS amplitude to the highest spurious component in the output spectrum, typically expressed in dBc or dBFS. In a time-interleaved ADC, interleaving mismatch spurs directly degrade SFDR. The specific frequencies and amplitudes of these spurs form a unique spectral pattern that can be used for device identification. Key characteristics include:

• Gain/offset spurs: Signal-independent or amplitude-dependent
• Timing skew spurs: Frequency-dependent amplitude
• Spur periodicity: Determined by the interleaving factor M

A class of techniques, including Data-Weighted Averaging (DWA), that spectrally shape the error caused by component mismatch in multi-bit converters. Rather than eliminating mismatch, these techniques move the distortion energy out of the band of interest and into higher frequencies. This creates a distinct, noise-shaped residual signature that is itself a unique hardware fingerprint. Understanding mismatch shaping is critical because it transforms static mismatch errors into a shaped noise profile that must be accounted for in any fingerprinting model.