A Sample-and-Hold Amplifier (SHA), also known as a track-and-hold, operates in two distinct modes. In sample (or track) mode, its output precisely follows the input analog signal. Upon receiving a clock command, it switches to hold mode, freezing the instantaneous voltage on a storage capacitor to provide a stable, time-invariant level for the downstream quantizer to digitize.
Glossary
Sample-and-Hold Amplifier (SHA)

What is a Sample-and-Hold Amplifier (SHA)?
A Sample-and-Hold Amplifier is a critical analog front-end circuit that captures an instantaneous voltage value and holds it constant for the duration of the analog-to-digital conversion cycle.
The non-idealities of this circuit are primary sources of a digitizer's unique hardware fingerprint. Aperture jitter introduces timing uncertainty at the sampling instant, while pedestal error and droop cause voltage offsets and decay during the hold period. These process-dependent imperfections create a distinct, unclonable signature exploitable for physical layer authentication.
Key Non-Idealities Exploited for RF Fingerprinting
The Sample-and-Hold Amplifier (SHA) is a critical front-end circuit that captures an instantaneous analog value and holds it steady for the subsequent quantizer. Its non-idealities—including pedestal error, droop, and aperture jitter—are primary sources of a digitizer's unique, unclonable signature.
Aperture Jitter & Timing Uncertainty
Aperture jitter is the sample-to-sample variation in the precise instant the SHA switch opens. This timing uncertainty modulates the phase of the digitized waveform, creating a unique, clock-related fingerprint.
- Mechanism: Noise in the sampling clock or switch driver causes the hold command to arrive slightly early or late.
- Impact: The voltage error is proportional to the signal's slew rate at the sampling instant. Higher frequency inputs suffer greater amplitude errors.
- Fingerprint: The resulting phase noise sidebands and non-uniform sampling artifacts are specific to the clock generation and distribution circuitry of a particular device.
Pedestal Error (Hold Step)
Pedestal error is an undesired DC voltage offset introduced at the output during the transition from sample mode to hold mode. It is primarily caused by charge injection and clock feedthrough from the sampling switch.
- Charge Injection: When the MOSFET switch turns off, the mobile charge in its channel is dumped onto the hold capacitor, causing a voltage step.
- Clock Feedthrough: The gate-drive clock signal couples through the gate-drain overlap capacitance directly to the hold capacitor.
- Fingerprint: This error is a function of the switch's exact physical dimensions, threshold voltage, and layout parasitics, making it a strong, static, device-specific DC bias.
Droop Rate & Hold Capacitor Leakage
Droop is the gradual decrease in the held output voltage over time during the hold mode. It is caused by leakage currents discharging the hold capacitor.
- Sources: Leakage through the off-state sampling switch, the input bias current of the output buffer amplifier, and the intrinsic dielectric absorption of the capacitor itself.
- Fingerprint: The droop rate (dV/dt) is highly dependent on temperature, semiconductor process variations, and the physical quality of the capacitor. This creates a time-dependent signature that can be measured over the ADC's conversion cycle.
Dielectric Absorption & Memory Effects
Dielectric absorption (or soakage) is a memory effect in the hold capacitor where a residual charge persists after a rapid voltage change, causing the held voltage to creep toward a previous value.
- Mechanism: Dipoles in the capacitor's dielectric material align slowly with the applied field and do not relax instantly when the field changes.
- Fingerprint: This introduces a history-dependent error, where the current held sample is contaminated by the voltage of prior samples. This dynamic non-linearity creates a complex, signal-correlated signature that is extremely difficult to clone or model without the exact physical component.
Acquisition Time & Slewing Distortion
Acquisition time is the finite interval required for the hold capacitor to charge to the input voltage and settle to within a specified error band. Non-linear slewing during this period creates distortion.
- Slewing: If the input buffer cannot supply enough current, the capacitor voltage changes at a fixed maximum rate (slew rate), causing a non-linear tracking error for large, fast input steps.
- Fingerprint: The specific slew-rate limit and the shape of the small-signal settling tail (often an underdamped ringing) are determined by the amplifier's compensation and parasitic poles, providing a unique transient signature.
Sampling Glitch & Kickback Noise
Kickback noise is a transient disturbance injected back into the input signal source when the sampling switch closes. The internal charge redistribution creates a high-frequency glitch.
- Mechanism: The sudden connection of the discharged hold capacitor to the input node causes a rapid current draw, which interacts with the source impedance to create a voltage spike.
- Fingerprint: The amplitude and spectral content of this glitch depend on the switch's on-resistance, the capacitor value, and the exact parasitic routing. This signature can be detected by analyzing the input signal's disturbance during the sampling instant.
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Frequently Asked Questions
Explore the fundamental operating principles and critical non-idealities of the Sample-and-Hold Amplifier, the front-end circuit whose imperfections form the bedrock of digitizer fingerprinting.
A Sample-and-Hold Amplifier (SHA), also known as a track-and-hold amplifier, is a critical analog front-end circuit that captures an instantaneous voltage value from a continuous-time input signal and maintains that value at a steady level for the duration required by a subsequent Analog-to-Digital Converter (ADC) to perform accurate quantization. The operation occurs in two distinct phases: during the track mode (or sample mode), a switch is closed, and a holding capacitor charges to follow the input signal; during the hold mode, the switch opens, isolating the capacitor so the stored voltage remains constant. This frozen value is then presented to the ADC, preventing the conversion error that would occur if the signal continued to change during the quantization process. The precision of this transition between tracking and holding is paramount, as any deviation from the ideal instantaneous capture directly introduces timing uncertainty and amplitude errors into the digitized representation.
Related Terms
Explore the critical converter non-idealities and signal processing concepts that, alongside the Sample-and-Hold Amplifier, define a digitizer's unique hardware fingerprint.
Aperture Jitter
The sample-to-sample variation in the precise instant the SHA captures a signal. This timing uncertainty modulates the phase of the digitized waveform, creating a unique, clock-related fingerprint. Aperture jitter is often the dominant source of high-frequency noise in a digitizer, directly limiting the achievable Signal-to-Noise Ratio (SNR) for fast-moving signals.
Pedestal Error & Droop
Two fundamental SHA-specific non-idealities. Pedestal error is an unwanted DC offset voltage introduced during the transition from sample to hold mode, caused by charge injection from the sampling switch. Droop is the gradual decay of the held voltage due to leakage currents, making the output value a function of hold time. Both are highly device-specific.
kT/C Noise
The fundamental thermal noise sampled onto the SHA's hold capacitor during the acquisition phase. The RMS noise voltage is determined by √(kT/C), setting a physical limit on the system's noise floor. Since the exact capacitance value varies with Process-Voltage-Temperature (PVT) shifts, the precise kT/C noise contribution is a unique, process-dependent signature of each chip.
Integral Non-Linearity (INL)
A measure of the overall static linearity of the entire digitizer chain, including the SHA's buffer amplifier. INL is the maximum deviation of the actual transfer function from an ideal straight line. The unique, smooth 'S-curve' or 'bow' shape of the INL profile is a highly process-dependent artifact that serves as a robust, low-frequency component of the device's fingerprint.
Dynamic Non-Linearity
Amplitude distortion with a dependence on signal history or frequency, encompassing effects like slew-rate limiting and memory effects in the SHA's output buffer. Unlike static INL, dynamic non-linearity introduces a complex, history-dependent signature that is exceptionally difficult to clone, making it a high-value feature for anti-spoofing systems.
Time-Interleaved ADC
An architecture using multiple parallel sub-ADCs, each with its own SHA, sampling in a round-robin sequence. Gain, offset, and timing mismatches between the parallel SHAs create deterministic, periodic spurs in the output spectrum. This interleaving mismatch produces a dominant, highly exploitable fingerprint that is easily detectable with spectral analysis.

About the author
Prasad Kumkar
CEO & MD, Inference Systems
Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.
His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.
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