Unified Power Format (UPF)

A power domain is a collection of design elements that share a common primary power supply and ground net. UPF uses the create_power_domain command to define these logical partitions. Domains can be hierarchical, allowing for complex, multi-voltage systems. For example, a system-on-chip (SoC) might have separate domains for a high-performance CPU cluster, a low-power always-on sensor hub, and various peripheral blocks, each with its own voltage requirements and power states.

Power states define the operational modes of a power domain, such as ON, OFF, or RETENTION. UPF specifies these states with the add_power_state command, creating a state table. This is crucial for modeling sequences like:

• Active Mode: Full voltage applied, domain fully functional.
• Sleep Mode: Voltage reduced (DVFS) or removed (power gating).
• Retention Mode: Main power off, but a small retention voltage applied to keep flip-flop states alive. These states drive the implementation of power switches, isolation, and level shifters.

Isolation is the insertion of special cells (isolation cells) at the outputs of a power domain that can be turned off. Their purpose is to prevent floating or unknown ('X') logic values from propagating to always-on domains, which could cause functional failure. UPF commands like set_isolation and set_isolation_control specify:

• Where to insert isolation (domain outputs).
• When it should be active (e.g., when the source domain is OFF).
• The clamp value (e.g., tie to 0, 1, or latch the last value).

Level shifters are cells required when signals cross between power domains operating at different voltage levels. A signal driven from a 0.8V domain cannot reliably switch a transistor in a 1.2V domain. UPF's set_level_shifter command directs the tool to automatically insert these cells at domain boundaries. Key attributes include:

• Direction: Specifies if shifting is needed for low-to-high voltage, high-to-low, or both.
• Location: Can be placed in the source domain, destination domain, or on both sides.
• Threshold: Defines the specific voltage translation required.

State retention allows a power domain to be powered down while preserving the logical state of specific registers (e.g., in a processor's context). UPF specifies this with set_retention. The strategy involves:

• Retention Registers: Special flip-flops with a separate, always-on power supply for the state storage element.
• Control Signals: Save and restore signals that trigger the capture and reload of state.
• Power Switches: Used to cut the main power rail while the retention supply remains active. This enables fast wake-up from sleep states without a full system reboot.

Power switches (or power gates) are transistors that connect or disconnect a power domain from its primary supply rail. UPF defines them with create_power_switch. They are the physical mechanism for power gating. Key specifications include:

• Switch Type: Header (connects to VDD) or footer (connects to VSS).
• Control Signal: The signal that turns the switch ON or OFF.
• Acknowledge Signal: An optional feedback signal indicating the power network is stable.
• Isolation Strategy: The switch control is often coordinated with the isolation and retention control signals to ensure a safe power sequence.

UPF provides a declarative language to define the power architecture of a chip independently from its functional description (e.g., RTL). Key constructs include:

• Power Domains: Logical groupings of logic that share a common power supply and can be switched on/off together.
• Supply Networks: The hierarchy of power supplies, switches, and regulators that deliver power to domains.
• Power States: The legal combinations of on/off and voltage levels for different domains.
• Power Mode Tables: Define the relationships between power states and functional modes of the design. This specification acts as a single source of truth for power management, consumed by all downstream EDA tools.

UPF files are read and interpreted by a suite of EDA tools at each stage of the design flow, enabling consistent power-aware implementation and verification.

• Logic Synthesis: Tools like Synopsys Design Compiler use UPF to insert isolation cells, level shifters, and retention registers during netlist generation.
• Place-and-Route: Physical implementation tools (e.g., Cadence Innovus, Synopsys IC Compiler II) use UPF to guide the placement of power switches, create power grids, and ensure proper connectivity for always-on vs. switched power nets.
• Formal Verification: Tools perform power-aware equivalence checking to ensure the power-managed netlist is functionally equivalent to the original RTL under all specified power states.
• Simulation: Power-aware simulators (e.g., Synopsys VCS, Cadence Xcelium) use UPF to model power supply behavior, allowing verification of power-up/down sequences and isolation logic.

UPF directives drive the automatic insertion of specialized cells required for advanced power management techniques:

• Isolation Cells: Placed at the outputs of a powered-down domain to clamp signals to a known safe value (logic 0, 1, or latch previous state), preventing corrupt data or crowbar current in receiving domains.
• Level Shifters: Inserted when signals cross between power domains operating at different voltage levels to ensure correct logic voltage thresholds.
• Retention Registers: Special flip-flops with a separate, always-on power supply that retain their state when the main power domain is shut off, enabling fast context restoration.
• Power Switches: Header (PMOS) or footer (NMOS) transistors that are controlled to connect or disconnect a power domain from its supply rail, implementing power gating. The toolchain uses UPF to determine the optimal placement and hookup of these cells.

UPF enables rigorous verification of power management logic, which is critical for functional correctness and preventing chip failures.

• Static Checks: Tools verify UPF syntax and semantics, check for unreachable power states, and validate supply network connectivity (e.g., no floating nets).
• Dynamic Simulation: Engineers write testbenches to simulate complex power state transitions, verifying that isolation and retention protocols work correctly and that no power sequencing violations occur.
• Formal Property Checking: Assertions can be written to formally prove that specific power management behaviors hold under all conditions, such as "when domain A is off, its outputs must be isolated."
• Electrical Rule Checking (ERC): Post-layout tools verify that the physical implementation adheres to electrical constraints related to power, such as IR drop analysis and electromigration checks on power grids.

UPF supports modern, block-based design methodologies.

• Hierarchical Power Intent: Power intent can be specified top-down, bottom-up, or in a mixed fashion. Block-level UPF can be written independently and then integrated at the top level, with tools resolving conflicts and ensuring consistency.
• Reuse and IP Integration: Semiconductor IP providers can deliver hard or soft macros with accompanying UPF files, clearly defining the block's power ports, internal domains, and requirements. This allows system integrators to seamlessly incorporate power-managed IP.
• Incremental Elaboration: Tools can re-elaborate the design with modified UPF without requiring a full re-synthesis from RTL, enabling rapid power architecture exploration and late-stage power intent changes. This flexibility is essential for large System-on-Chip (SoC) designs involving multiple teams and third-party IP.

UPF operates at the chip implementation level but connects to broader system power management frameworks.

• Interface with ACPI: The power states defined for processor cores in UPF (e.g., power gated, retention) are often mapped to the C-states and P-states managed by the operating system via the Advanced Configuration and Power Interface (ACPI). The firmware/software uses these states to command hardware power transitions.
• Firmware Coordination: On ARM-based systems, the Power State Coordination Interface (PSCI) in trusted firmware issues commands that trigger the power sequences described and implemented via UPF.
• Power Management Unit (PMU): The hardware PMU, often a separate microcontroller on the SoC, executes finite state machines that control the sequencing of power switches, retention, and isolation—all of which are implemented based on the UPF specification. Thus, UPF provides the hardware realization of the power management policies defined at the system architecture level.

A fundamental low-power technique where power is completely shut off to an idle circuit block using header or footer switches. UPF specifies the power switches, their control signals, and the isolation cells needed to safely gate power.

• Eliminates both dynamic and leakage power in the gated domain.
• Requires careful sequencing: save state, isolate outputs, then power down.
• UPF commands: create_power_switch, set_isolation.

A runtime power management technique that dynamically adjusts a processor's operating voltage and clock frequency based on workload demand. UPF defines the power domains and supply sets that support multiple voltage levels.

• Trade-off performance for power efficiency.
• Requires level shifters (specified in UPF) for signals crossing between voltage domains.
• Managed by the OS/PMU using standards like ACPI P-states.

An advanced form of power gating where the main power supply to a block is cut off to eliminate leakage, but a small, separate retention supply keeps critical flip-flop states alive. UPF specifies the retention strategy and control signals.

• Enables ultra-fast power-up as logic state is preserved.
• UPF commands: set_retention, map_retention_cell.
• Essential for always-on, instant-wake subsystems in mobile SoCs.

The open industry standard (led by Intel, Microsoft, Toshiba) that defines power management interfaces between the operating system and platform firmware. UPF provides the implementation intent for the hardware power states that ACPI manages.

• ACPI defines the 'what' (system sleep states S0-S5, processor P-states/C-states).
• UPF defines the 'how' (power domains, switches, isolation for those states).
• The OS uses ACPI tables to call firmware methods that trigger UPF-defined power sequences.

A dedicated hardware controller, often a microcontroller or finite state machine, that executes the low-level power sequencing defined by UPF. It controls power switches, isolation, retention, and level shifter enable signals.

• The physical executor of UPF intent.
• Manages safe power-up/down sequences to avoid current spikes and data corruption.
• Interfaces with the main processor and external voltage regulators.

The engineering discipline focused on delivering stable, clean power to all transistors on a chip. UPF-defined power domains and switches directly impact power distribution network (PDN) design and integrity.

• UPF informs PDN design by specifying current requirements per domain.
• Challenges include managing in-rush current during power-up and voltage droop during activity.
• Poor integrity can cause timing violations or functional failures, even with correct UPF.