Power Integrity

Voltage droop is a transient or sustained drop in the supply voltage delivered to a transistor due to resistance (IR) and inductance (L di/dt) in the power delivery network. This is critical during sudden high-current demand events, such as when many NPU cores switch simultaneously. Excessive droop can cause:

• Timing violations as logic gates slow down.
• Functional failures if voltage falls below the minimum operational level. Mitigation involves dense on-chip power grids, strategically placed decoupling capacitors, and low-impedance package interconnects.

Ground bounce, the reciprocal of voltage droop, is a rise in the local ground reference voltage caused by the inductance of ground return paths when many output drivers switch simultaneously. This effectively reduces the voltage seen by gates and can cause:

• False switching in quiet circuits.
• Increased signal integrity issues and crosstalk. It is managed through careful package and board design to minimize inductance, using multiple dedicated ground pins, and implementing on-die termination schemes.

Power supply noise encompasses all high-frequency voltage fluctuations on the power rail, originating from sources like switching voltage regulators, digital clock harmonics, and coupling from adjacent signals. This noise directly modulates gate delays, creating jitter that degrades timing margins. Key management techniques include:

• Multi-stage filtering using a hierarchy of bulk, ceramic, and on-die capacitors.
• Separate analog and digital power domains to isolate sensitive circuits.
• Careful PCB layout with dedicated power planes and minimized current loop areas.

Decoupling capacitors are the primary tool for combating power integrity issues by providing localized charge reservoirs. Their effectiveness depends on a hierarchical strategy across the PDN:

• Bulk capacitors (10-100µF) on the board handle low-frequency droop.
• Ceramic capacitors (0.1-1µF) near the package address mid-frequency noise.
• On-die capacitance (nF range) is integrated into the silicon to counter ultra-high-frequency, nanosecond-scale transients. The challenge lies in managing the parasitic inductance of the capacitor's mounting, which limits its effective frequency range.

The fundamental goal of power integrity design is to minimize the impedance of the Power Delivery Network (PDN) across a broad frequency spectrum, from DC to gigahertz. The PDN impedance, Z(f), determines the voltage noise for a given current transient: ΔV = I * Z. Key design targets include:

• Achieving a target impedance (often in the milliohm range) based on the chip's current profile.
• Ensuring the impedance profile remains below this target across all relevant frequencies. This requires co-design of voltage regulators, package parasitics, and on-chip grid resistance.

Modern NPUs exhibit extreme transient current demand (di/dt), where current draw can change by tens of amps within nanoseconds when computational kernels start or stop. This rapid change, combined with PDN inductance, is the primary source of voltage droop and ground bounce. Managing di/dt involves:

• Clock staggering to spread out switching events.
• Microarchitectural techniques like pipeline gating.
• Advanced packaging (e.g., 2.5D/3D) to bring regulators closer to the die.
• Silicon measurement using embedded sensors to characterize and model the true current waveform.

The Power Delivery Network (PDN) is the complete electrical pathway that supplies stable voltage from the system power supply to the individual transistors on an NPU die. It includes:

• Voltage Regulator Modules (VRMs) and Low-Dropout Regulators (LDOs) for conversion.
• Package-level interconnects and on-die power grids.
• Decoupling capacitors to filter high-frequency noise and provide localized charge. A poorly designed PDN leads to voltage droop and ground bounce, directly causing the timing errors and functional failures that power integrity engineering aims to prevent.

Dynamic Voltage and Frequency Scaling (DVFS) is a runtime power management technique that adjusts a processor's operating voltage and clock frequency in tandem based on instantaneous workload demand. It is a primary tool for managing dynamic power, which scales with the square of the voltage (P ∝ V²f).

• P-States (Performance States) are the ACPI-defined operating points for DVFS.
• By lowering voltage/frequency during low-utilization periods, DVFS dramatically reduces power consumption and heat generation.
• It introduces a critical trade-off: aggressive voltage scaling can bring the operating point closer to the minimum functional voltage, increasing sensitivity to power integrity noise.

Power gating is a circuit-level technique that uses header or footer switches to completely disconnect a logic block from the power or ground rail when idle. This is the most effective method to eliminate leakage power (static power), which becomes dominant at advanced process nodes.

• State Retention Power Gating (SRPG) is an advanced form where a small, always-on power domain retains the block's register states, allowing for fast wake-up.
• The Unified Power Format (UPF) is the standard language for specifying power intent, including power domains for gating.
• Sudden inrush current when a gated block wakes up can cause significant local voltage droop, a key power integrity challenge during design verification.

Thermal Design Power (TDP), specified in watts, is the maximum sustained power a cooling system is designed to dissipate for a chip under a defined workload. It is a cornerstone for system-level power budgeting.

• Thermal throttling is the protective response when a chip's temperature exceeds safe limits. It triggers DVFS to lower frequency/voltage or activates power gating to reduce heat generation, directly sacrificing performance for reliability.
• Dynamic Thermal Management (DTM) systems proactively monitor temperature (via on-die sensors) and apply throttling or workload migration to stay within the Thermal Safe Operating Area (SOA).
• Power integrity ensures stable voltage during these aggressive thermal management transitions.

Performance per watt is the primary efficiency metric for accelerators like NPUs, measuring computational throughput (e.g., FLOPS) divided by power consumption (Watts).

• The Energy-Delay Product (EDP) is a more nuanced metric that balances energy consumption and execution time (Energy × Delay). Optimizing for EDP often means running at a lower voltage/frequency point than peak performance.
• These metrics are the ultimate benchmarks for power management techniques. Effective power integrity is non-negotiable for achieving high scores, as voltage noise reduces both performance (causing errors/retries) and efficiency.

Process-Voltage-Temperature (PVT) corners represent the extreme combinations of manufacturing variations, supply voltage fluctuations, and operating temperature ranges used during chip design verification.

• 'Fast' corners (fast transistors, high voltage, low temperature) check for maximum performance and potential timing violations.
• 'Slow' corners (slow transistors, low voltage, high temperature) check for minimum functional voltage and setup time failures.
• Power integrity analysis must be performed across these corners to guarantee the Power Delivery Network (PDN) provides stable voltage under worst-case voltage droop and ground bounce scenarios, ensuring the chip works in all real-world conditions.