Power State Coordination Interface (PSCI)

The CPU_SUSPEND function places a specific CPU core into a low-power idle state. The calling core provides a power state parameter defining the target C-state (e.g., WFI, retention, power down). The firmware saves the core's context and powers down components before entering the state. Upon a wake-up event, firmware restores context and returns control.

• Key Use: Managing core idle during OS scheduler inactivity.
• State Coordination: Must be coordinated with other cores to maintain cache coherency.
• Wake-up Sources: Can be configured for interrupts, timers, or inter-processor interrupts from other cores.

The CPU_ON function is used to power on and boot a secondary CPU core that is currently in a powered-down state. The calling core (typically the boot CPU) specifies the target core's MPIDR (Multiprocessor Affinity Register) and the entry point address for its execution. The trusted firmware handles the power sequencing, initializes the core, and starts it executing at the given address.

• Core Hotplug: Enables dynamic addition of CPU cores to the operating system's scheduler.
• Asynchronous Operation: The call returns immediately; completion is signaled via a separate mechanism.
• Boot Protocol: Follows the ARM boot architecture for initializing cores from a reset state.

The SYSTEM_SUSPEND function initiates a system-wide low-power state, such as suspend-to-RAM (STR). The OS prepares all devices and drivers, then calls this function. Firmware saves the entire system state to a predefined memory location, places DRAM into self-refresh, and powers down most SoC components. Resume is triggered by an external event (e.g., RTC alarm, button press), after which firmware restores the full system context.

• Deepest System State: Achieves the lowest power consumption while maintaining volatile memory.
• OS Coordination: Requires the OS to quiesce all I/O and save device states beforehand.
• Entry Address: The resume entry point (often in firmware) is specified in the call.

These functions manage system shutdown and restart. SYSTEM_RESET triggers a warm reset, rebooting the system. SYSTEM_OFF performs a cold shutdown, powering the system down completely; it requires an external event (like a power button) to restart.

• SYSTEM_RESET: Used for software-initiated reboots. Firmware may log the reset reason before re-initializing hardware.
• SYSTEM_OFF: The final power management call. Firmware signals the PMIC to remove main power rails. No state is preserved.
• PSCI 1.0+: These functions supersede the older SYSTEM_REBOOT and SYSTEM_SHUTDOWN calls.

AFFINITY_INFO queries the power state of a CPU core or a cluster of cores, reporting if it is ON, OFF, or ON_PENDING. CPU_FREEZE is a precursor to SYSTEM_SUSPEND that requests all cores to enter a coordinated, platform-specific low-power state without a full context save, useful for very low-latency sleep modes.

• Topology Discovery: AFFINITY_INFO helps the OS map the power domain hierarchy.
• Latency-Sensitive Sleep: CPU_FREEZE enables rapid system sleep/wake cycles for always-on applications.
• State Coordination: Both functions are essential for managing power domains above the individual core level.

PSCI functions are invoked via the Secure Monitor Call (SMC) or Hypervisor Call (HVC) instruction, depending on the system's exception level (EL) configuration. The calling convention is defined by the ARM Secure Monitor Call Calling Convention (SMCCC). The PSCI_FEATURES function allows a caller to check if a specific PSCI function is implemented and query its capabilities.

• Standardized Invocation: SMCCC defines register usage for function IDs and return values.
• Version Discovery: PSCI_VERSION returns the implemented interface version (e.g., 1.0, 1.1, 2.0).
• Extensibility: PSCI_FEATURES enables forward compatibility, allowing new functions to be queried safely.

A Power Management Unit (PMU) is a dedicated hardware controller, often a microcontroller core within a System-on-Chip (SoC), responsible for executing low-level power sequences. It acts as the physical enforcer for commands issued via PSCI.

• Functions: Controls power gating switches, sequences voltage ramp-up/down via Voltage Regulator Modules (VRMs), manages clock distribution, and handles wake-up events from peripherals.
• Relationship to PSCI: The PSCI interface in the ARM Trusted Firmware translates OS requests (e.g., CPU_OFF) into commands for the SoC-specific PMU, which then performs the precise electrical sequencing.

Dynamic Voltage and Frequency Scaling (DVFS) is the primary technique for active power management, dynamically adjusting a processor core's operating voltage and clock frequency in response to workload demand. It is a key mechanism invoked through PSCI or ACPI P-State interfaces.

• Principle: Lowering frequency and voltage quadratically reduces dynamic power (P ∝ C * V² * f).
• Coordination: The OS scheduler or a runtime governor requests a performance level. PSCI provides the CPU_SET_PERFORMANCE_STATE function to instruct the firmware and PMU to apply the new voltage-frequency pair.

C-States (idle) and P-States (active) are the fundamental abstractions for processor power management that PSCI and ACPI implement.

• C-States (Core Sleep States): Define how deeply a core powers down when idle. C0 is active; C1 (WFI) halts the clock; deeper states like C6 flush caches and power-gate the core. PSCI functions like CPU_SUSPEND enter these states.
• P-States (Performance States): Define active operating points (voltage/frequency pairs) for a core. P0 is max performance; P1, P2, etc., are lower-power states. PSCI's CPU_SET_PERFORMANCE_STATE manages these.
• System-Level States: Corresponding S-States (e.g., S3/suspend-to-RAM) are managed by higher-level PSCI SYSTEM_SUSPEND calls.