Adaptive Voltage Scaling (AVS)

Unlike static or open-loop methods, AVS implements a real-time feedback loop. A performance monitor (e.g., a ring oscillator or critical path replica) on the silicon measures actual circuit speed. This measurement is compared against a target frequency, and a digital controller (often a PID controller) commands the voltage regulator to increase or decrease the supply voltage (Vdd) accordingly. This continuous adjustment ensures the minimum voltage required for stable operation at the current frequency and silicon condition.

Modern AVS implementations operate at fine granularity. Instead of applying one voltage to an entire chip, AVS can control voltage domains for individual processor cores, NPU tiles, or other functional blocks. This allows for:

• Independent voltage scaling based on each domain's specific workload.
• Power gating of idle domains without affecting others.
• More precise optimization, as a heavily loaded NPU core can receive higher voltage while an idle CPU core remains at a lower voltage, reducing overall system power.

The primary efficiency gain of AVS comes from eliminating conservative voltage guardbands. Traditional designs use a fixed, worst-case voltage to cover:

• Process variation (fast vs. slow silicon across wafers).
• Voltage droop (temporary dips in supply voltage).
• Temperature variation (circuits slow down at high temperatures).
• Aging effects (transistor performance degrades over time). AVS dynamically compensates for these factors in real-time, allowing the voltage to be set just above the minimum required for the actual silicon, at the current temperature, thereby saving 20-40% dynamic power compared to static worst-case scaling.

AVS is typically used in conjunction with Dynamic Voltage and Frequency Scaling (DVFS). The relationship is hierarchical:

1. The OS or PMU selects a target Performance State (P-state) with a specific frequency.
2. The AVS system then determines and applies the minimum stable voltage for that frequency on the specific core. It also interacts with idle Power States (C-states). When a core enters a deep C-state, AVS can command the voltage regulator to ramp down to a retention voltage or to zero, working in tandem with power gating.

AVS requires per-chip calibration, often performed during manufacturing test or at boot. This process characterizes the unique Process-Voltage-Temperature (PVT) behavior of each individual die. Key calibrated parameters include:

• Fmax(V) curves: The maximum frequency achievable at a given voltage.
• Sensor calibration: Adjusting the on-die performance monitors for accuracy.
• Controller coefficients: Tuning the feedback loop for stability and response time. This calibration data is stored in fuses or non-volatile memory and used by the AVS controller firmware to make correct voltage decisions.

AVS is a foundational technology for energy-constrained devices like smartphones, IoT sensors, and autonomous vehicles. Its value is magnified for Neural Processing Units (NPUs) which experience highly variable workloads—from bursty inference to sustained training. Benefits include:

• Extending battery life by minimizing power during low-utilization periods.
• Enabling higher sustained performance within a fixed Thermal Design Power (TDP) or power budget by avoiding thermal throttling longer.
• Improving performance per watt, a key metric for evaluating edge AI accelerators.

AVS operates as a real-time feedback control system. It continuously monitors the processor's actual performance and silicon characteristics using on-die performance monitors and critical path replicas. Based on this telemetry, a Power Management Unit (PMU) or dedicated controller dynamically adjusts the supply voltage from the Voltage Regulator Module (VRM). This closed-loop approach contrasts with open-loop Dynamic Voltage and Frequency Scaling (DVFS), which uses pre-characterized voltage-frequency tables, allowing AVS to compensate for Process-Voltage-Temperature (PVT) variations and aging effects in real-time.

The precision of AVS depends on specialized hardware for in-situ measurement.

• Ring Oscillators (ROs): Circuits whose oscillation frequency correlates with transistor speed, providing a proxy for process and temperature conditions.
• Critical Path Replicas (CPRs): Miniature copies of the processor's slowest timing paths. By testing these paths with a margin, the system determines the minimum viable voltage.
• Error-Detection Sequential (EDS) circuits: Special flip-flops that can detect timing errors, allowing the system to operate at the razor-thin edge of failure and then slightly increase voltage.
• Temperature Diodes: Provide direct junction temperature readings to the PMU.

These sensors feed data to the control algorithm, enabling per-chip and real-time optimization.

The intelligence of AVS resides in its control logic, which processes sensor data to issue voltage commands.

• Proportional-Integral-Derivative (PID) Controllers: Common in analog AVS implementations, they adjust voltage based on the error between a target performance (e.g., ring oscillator frequency) and the measured value.
• Digital Look-Up Table (LUT) & Search Algorithms: Used in digital AVS. The system performs periodic margin searches—briefly lowering voltage, testing CPRs for errors, and settling at the last safe voltage.
• Machine Learning-Based Controllers: Emerging approach where models predict optimal voltage based on multi-sensor input, workload history, and thermal state.

The algorithm's aggressiveness trades off between power savings and the risk of timing violations.

AVS does not operate in isolation; it integrates with broader power management infrastructure.

• Coordination with DVFS: While DVFS changes the frequency-voltage (V-f) curve, AVS dynamically slides along the curve, minimizing the voltage for a given frequency target. They are complementary techniques.
• Interaction with C-States/P-States: During deep C-States, AVS may be disabled as the core is powered off. On wake-up or P-State transition, AVS rapidly converges to the optimal voltage for the new operating point.
• Power Budgeting & RAPL: AVS actions are often constrained by higher-level limits like Running Average Power Limit (RAPL). The system may prioritize meeting a power cap over maximizing AVS savings.

AVS is critical in battery-powered devices where energy efficiency and Performance per Watt are paramount.

• Smartphones & Tablets: Extends battery life by reducing CPU, GPU, and NPU power during variable workloads (e.g., scrolling, video playback, background tasks).
• IoT Sensors & Wearables: Enables operation within extremely tight power budgets, often leveraging AVS to compensate for wide temperature ranges in harsh environments.
• Drones & Robotics: Manages power for extended flight/operation times while handling bursty computational loads for navigation and sensing.

Here, AVS directly counters Dark Silicon limitations by allowing more transistors to be active within a fixed thermal envelope.

In performance-driven environments, AVS targets power and cooling cost reduction and maximizing throughput within a fixed Thermal Design Power (TDP).

• Server CPUs & AI Accelerators: Manages leakage power, which becomes dominant at advanced process nodes. AVS tailors voltage per core or cluster based on its unique PVT corner, improving yield and binning.
• High-Performance Computing (HPC): Allows clusters to operate closer to their thermal limits (Thermal Safe Operating Area) by minimizing unnecessary voltage guardbands, increasing aggregate performance.
• Mitigating Voltage Droop: Fast AVS controllers can react to Power Integrity events like sudden voltage droop, temporarily boosting voltage to prevent errors, allowing for a more aggressive baseline PDN design.

This application is key for managing the Power Delivery Network (PDN) in large, heterogeneous chips.

Dynamic Voltage and Frequency Scaling (DVFS) is the foundational open-loop technique upon which AVS builds. It dynamically adjusts a processor's operating voltage and clock frequency based on predicted workload demands from the operating system.

• Key Difference: DVFS uses pre-characterized voltage-frequency (V-F) tables, while AVS uses real-time silicon feedback to determine the minimum safe voltage.
• Operation: The OS or driver selects a performance state (P-state), and the hardware applies the corresponding V-F pair from a static table.
• Guardband: Requires significant voltage margins to account for worst-case Process, Voltage, and Temperature (PVT) variations, leading to less optimal efficiency than AVS.

The Power Delivery Network (PDN) is the critical physical infrastructure that enables techniques like AVS. It comprises the entire path delivering clean, stable power from the voltage regulator to the individual transistors on the NPU die.

• Components: Includes Voltage Regulator Modules (VRMs), package interconnects, on-die power grids, and decoupling capacitors.
• AVS Dependency: AVS requires an extremely responsive PDN to execute rapid, fine-grained voltage adjustments without causing destructive voltage droops or overshoots (power integrity issues).
• Design Challenge: The PDN's impedance must be managed across a wide frequency range to support the swift transitions demanded by closed-loop AVS controllers.

Process-Voltage-Temperature (PVT) Corners represent the extreme environmental and manufacturing variations that traditional design must guard against. AVS directly mitigates the inefficiencies caused by these guardbands.

• Definition: The worst-case combinations of semiconductor process speed (Fast/Slow), supply voltage (Min/Max), and operating temperature (Min/Max) used during chip sign-off.
• Static Guardband: A fixed-voltage system must supply enough voltage to ensure functionality at the 'slow' process, 'low' voltage, 'high' temperature corner—which is excessive for most chips under normal conditions.
• AVS Advantage: By sensing actual silicon performance, AVS dynamically adjusts voltage for the chip's specific process characteristics and instantaneous temperature, effectively 'shrinking' the PVT space that must be covered.

Performance per watt is the paramount efficiency metric that AVS is designed to improve. It quantifies the computational work accomplished per unit of electrical energy consumed.

• Calculation: Typically measured in operations per second per watt (e.g., TOPS/W) or a similar task-specific metric.
• AVS Impact: Because dynamic power is proportional to the square of the voltage (P ∝ V²), even small reductions in operating voltage yield significant power savings. By minimizing voltage guardbands, AVS directly increases performance per watt for a given workload.
• System-Level Effect: Improved performance per watt at the core level translates to higher aggregate computational density within a fixed Thermal Design Power (TDP) or power budget for the entire system.

The Power Management Unit (PMU) is the dedicated hardware controller that typically implements AVS logic. It is a critical block within a System-on-Chip (SoC) or NPU.

• Function: The PMU sequences power domains, controls voltage regulators, manages clock sources, and handles sleep state transitions. It hosts the Advanced Configuration and Power Interface (ACPI) or Power State Coordination Interface (PSCI) firmware.
• AVS Implementation: For AVS, the PMU integrates the critical path monitor sensors, reads their performance signatures, and issues commands to the Voltage Regulator Module (VRM) to adjust the core supply voltage.
• Integration: It works in concert with the operating system's demand for Performance States (P-States) but uses its closed-loop feedback to determine the precise voltage, rather than relying on a static OS request.

AVS primarily targets the reduction of dynamic power, which is one of the two main components of total chip power consumption.

• Dynamic Power: The power consumed by charging and discharging capacitive loads during transistor switching. Its formula is P_dynamic = α * C * V² * f, where α is activity, C is capacitance, V is voltage, and f is frequency. AVS reduces this by lowering V.
• Leakage Power (Static Power): The power dissipated due to unwanted subthreshold and gate leakage current when transistors are idle. It is highly sensitive to voltage and temperature.
• AVS Interaction: While focused on dynamic power, lowering V with AVS also reduces leakage power. However, deep idle states are managed separately by techniques like Power Gating and C-States, which the PMU also controls.