Performance States (P-States)

P-States are formally defined by the Advanced Configuration and Power Interface (ACPI) specification. This provides a standardized, OS-directed interface for power management.

• P0: The highest performance state, operating at the base or turbo frequency and voltage.
• P1 to Pn: Successively lower performance states, each with reduced frequency and voltage.
• The operating system's CPU governor (e.g., intel_pstate, acpi-cpufreq) selects the appropriate P-State based on workload demand and policy.

A P-State defines a specific pairing of clock frequency and core voltage. This coupling is fundamental to power management.

• Dynamic Power scales with the square of the voltage (P ∝ V² * f). Lowering both parameters dramatically reduces power consumption.
• The relationship is non-linear; voltage must be high enough to support stable operation at a given frequency. This voltage-frequency curve is characterized during silicon manufacturing.
• Modern processors use Adaptive Voltage Scaling (AVS) to minimize voltage guardbands for each frequency step, improving efficiency beyond static tables.

P-State control can be applied at different levels of hardware granularity, affecting scalability and power savings.

• Per-Core P-States: Modern architectures allow independent P-State control for each CPU core, enabling fine-grained power management.
• Per-Cluster P-States: In some SoC designs, a group of cores (a cluster) shares a voltage domain and must transition together.
• Uncore/System Agent: Separate P-States may exist for non-core parts of the processor, like the last-level cache, memory controller, and graphics unit.

Switching between P-States incurs a time and energy cost, which influences governor policy.

• Latency: Transitioning involves locking the phase-locked loop (PLL) to a new frequency and stabilizing the voltage regulator. This can take 10-100 microseconds.
• Granularity: The number of discrete P-States available. Modern processors have many fine-grained steps (e.g., 100 MHz increments), allowing smoother performance scaling.
• Governors must weigh the energy saved by entering a lower P-State against the energy and performance cost of the transition itself.

P-States operate within the broader ACPI power management hierarchy, primarily interacting with C-States and system-level states.

• C-States (Idle): P-States govern active power. When a core is idle, it first enters a low P-State (often Pn), then may enter a deeper C-State to power-gate circuits and reduce leakage.
• System States (S-States): During system sleep (S3/Suspend-to-RAM), all cores are powered down, making P-States irrelevant.
• Throttling States (T-States): An older, cruder throttling mechanism largely superseded by fine-grained P-States.

P-State control is implemented through a collaboration of hardware interfaces and firmware.

• Model-Specific Registers (MSRs): The primary hardware interface. The OS writes to MSRs (e.g., IA32_PERF_CTL) to request a P-State.
• ACPI _PSS Objects: The firmware provides the _PSS (Performance Supported States) table, listing the available frequency/voltage/power tuples to the OS.
• Power Control Unit (PCU): A dedicated microcontroller on modern Intel CPUs that manages the final P-State transition, thermal limits, and turbo algorithms.

Performance per watt is the fundamental efficiency metric that P-States are designed to optimize. It quantifies the computational work accomplished per joule of energy consumed.

• Calculation: Typically measured as throughput (e.g., inferences/second, FLOPS) divided by average power draw (watts).
• P-State Optimization: The OS governor's goal is to select the P-State that delivers the required performance at the lowest possible power, maximizing this ratio.
• System Impact: Drives design trade-offs in Dark Silicon, where not all transistors can be active simultaneously due to power delivery network and thermal limits, making intelligent P-State scheduling essential.