High-Level Synthesis (HLS)

Hardware microarchitecture is steered using synthesis pragmas (directives) embedded in the source code. Key directives include:

• PIPELINE: Overlaps loop iterations to increase throughput, trading off resource usage.
• UNROLL: Partially or fully flattens loops to create parallel hardware instances.
• ARRAY_PARTITION: Splits BRAM arrays into multiple banks to eliminate memory access bottlenecks.
• DATAFLOW: Enables task-level pipelining between sequential functions. This allows a single C++ function to be synthesized into a low-area serial engine or a high-throughput parallel datapath without rewriting the algorithm.

HLS tools natively support the AXI4-Stream protocol for high-throughput, flow-controlled data transfer. Declaring a function parameter as hls::stream<T> automatically generates the valid/ready handshake signals required for glueless integration into a streaming FPGA datapath. This is critical for wideband signal processing where a continuous flow of samples from a JESD204C ADC interface must be processed without backpressure stalls, enabling direct connection to channelizers and FFT cores.

HLS automatically manages pipeline balancing and handshake synchronization across hierarchical modules. When a function is pipelined with an Initiation Interval (II), the tool inserts the necessary shift registers and control logic to maintain data ordering. This is essential for implementing complex wideband DSP chains like a decimation chain with CIC and FIR stages, where each filter has a different pipeline depth. The designer focuses on the dataflow graph, while the tool ensures deterministic latency and phase coherency across all parallel channels.

The traditional hardware description abstraction that HLS seeks to replace. RTL design involves explicitly specifying the data flow between registers and the combinational logic operations performed at each clock cycle using languages like Verilog or VHDL. Unlike HLS, which focuses on algorithmic intent, RTL requires the designer to manually manage clock-level timing, pipelining, and finite state machines.

• Key Distinction: HLS compiles behavior; RTL describes micro-architecture.
• Use Case: Still dominant for ultra-fine-grained optimization of critical paths.

An ARM standard unidirectional point-to-point protocol designed for high-throughput streaming data transfer between IP cores in an FPGA or SoC. In HLS workflows, function arguments are often automatically mapped to AXI4-Stream interfaces to enable direct connection to other streaming IP blocks without buffering overhead.

• Mechanism: Uses a TVALID/TREADY handshake for back-pressure control.
• HLS Relevance: Essential for building dataflow pipelines where one function feeds directly into the next.

A double-buffering technique using two memory blocks where one is filled with input data while the other is being processed, enabling continuous streaming without stalls. HLS tools often infer or allow explicit instantiation of ping-pong buffers to overlap data transfer with computation.

• Benefit: Maximizes throughput by hiding memory access latency.
• HLS Directive: Typically implemented via array partitioning and dataflow pragmas.

The process of mapping continuous or high-precision values to a discrete integer representation with a fixed binary point, essential for efficient FPGA and ASIC implementation. HLS tools rely on arbitrary-precision fixed-point types to allow designers to trade off between dynamic range and resource utilization without the overhead of floating-point units.

• Example: ap_fixed<16,8> defines a 16-bit word with 8 integer bits.
• Impact: Directly determines DSP slice usage and logic depth.

An iterative shift-and-add algorithm for computing trigonometric, hyperbolic, and logarithmic functions. It is widely used in digital signal processing for efficient vector rotation and phase calculation because it avoids expensive multipliers. HLS libraries often provide optimized CORDIC implementations that synthesize to highly efficient LUT-based or DSP-based architectures.

• Advantage: Eliminates the need for large lookup tables or floating-point cores.
• Application: Critical for digital down conversion and IQ imbalance correction.

The transfer of a signal between two asynchronous clock domains in a digital circuit, requiring synchronization techniques to prevent metastability. While HLS abstracts away much of the low-level timing, understanding CDC is critical when integrating HLS-generated IP into a larger system with multiple clock sources.

• Risk: A single unsynchronized crossing can cause non-deterministic system failure.
• Mitigation: Use of dual-flop synchronizers or asynchronous FIFOs at the boundaries.