Clock Domain Crossing

The most fundamental single-bit synchronization circuit. A signal from the source domain is passed through a chain of two back-to-back flip-flops clocked by the destination domain. The first stage may enter a metastable state (oscillating or undefined voltage), but the second stage provides a full clock cycle for the signal to resolve to a valid logic level before it propagates further.

• Mean Time Between Failures (MTBF) increases exponentially with added stages.
• Suitable for slow, non-critical control signals.
• Does not guarantee data coherency for multi-bit buses.

A binary numeral system where successive values differ by only a single bit. Used for passing multi-bit values (like FIFO pointers) across clock domains. Since only one bit changes per transition, a synchronizer capturing a stale or new value will never sample an intermediate, wildly incorrect state.

• Eliminates the need for data path synchronization on the bus.
• Essential for asynchronous FIFO pointer handshakes.
• Converts to/from binary using simple XOR logic.

A First-In, First-Out memory buffer with independent read and write clocks. Data is written into the buffer using the source clock and read out using the destination clock. Gray-coded pointers are synchronized across the domain to generate empty/full flags without stalling the pipeline.

• Standard solution for high-throughput streaming data.
• Depth calculation depends on burst size and clock frequency ratios.
• Requires careful handling of pointer wrap-around logic.

A closed-loop request-acknowledge protocol for transferring data without a shared clock. The source asserts a REQ signal and holds data stable. The destination synchronizes REQ, captures the data, and asserts an ACK signal back to the source.

• Guarantees safe transfer regardless of clock phase/frequency.
• Low throughput due to round-trip latency.
• Ideal for register configuration or control state transfers.

A synchronization method for multi-bit data buses that avoids Gray code conversion. A control pulse is generated in the source domain, synchronized to the destination using a standard flip-flop chain, and used to enable a register that captures the stable data bus.

• The data bus must be held stable for the duration of the synchronization.
• Relies on setup and hold timing relative to the synchronized pulse.
• Simpler than FIFO for infrequent, bursty data transfers.

Specialized standard-cell flip-flops designed with higher gain-bandwidth product and optimized feedback loops to resolve metastable conditions faster than standard registers. They drastically improve MTBF in high-reliability applications.

• Reduces the required number of synchronizer stages.
• Critical for aerospace, automotive, and medical ASICs.
• Often characterized by specific tau (τ) and Tw resolution time constants.

The fundamental physical phenomenon that makes CDC necessary. When a flip-flop's input changes too close to the active clock edge, its output can enter an indeterminate voltage state that oscillates before settling to a valid logic level. This settling time is unbounded and can cause downstream logic to interpret different values, leading to non-deterministic system failure. Synchronizers are designed to give the signal time to resolve.

The most basic and widely used CDC structure. A signal from the source clock domain passes through two cascaded flip-flops clocked by the destination domain. This provides one full destination clock cycle for the first flop's potential metastable output to resolve before being captured by the second flop. Critical parameters include:

• MTBF (Mean Time Between Failures): Calculated based on clock frequency, toggle rate, and flop characteristics
• Only suitable for single-bit control signals, never for multi-bit data buses

The standard technique for safely passing multi-bit counter values across clock domains in an asynchronous FIFO. The binary read and write pointers are converted to Gray code before crossing, ensuring only a single bit changes per increment. This guarantees that a metastable sample on the destination side will be at most one count old, preventing catastrophic FIFO overflow or underflow. The Gray-to-binary conversion occurs after synchronization.

Standard STA tools assume all paths are synchronous and timed to a single clock. CDC paths are intentionally asynchronous and must be excluded from normal timing constraints using set_false_path or set_clock_groups -asynchronous. However, this creates a verification gap. Specialized CDC tools perform structural analysis to:

• Verify the presence and correctness of synchronizer structures
• Check for reconvergence of signals that crossed domains separately
• Ensure data bus stability during sampling windows

Multi-bit data buses cannot use simple two-flop synchronizers due to bit-skew where individual bits settle at different times. Two common solutions exist:

• Full Handshake: Uses request and acknowledge signals synchronized with two-flop chains to guarantee data stability before sampling
• MUX Recirculation: A control signal synchronized via two-flops enables a multiplexer to hold stable data, often used with FIFOs Both methods rely on the destination domain sampling only after the source confirms data is stable.

Mean Time Between Failures quantifies the reliability of a synchronizer chain. The formula incorporates:

• τ (tau): The resolution time constant of the destination flip-flop, a process-specific parameter
• T_w: The metastability window, the time interval around the clock edge where a data change triggers metastability
• f_c and f_d: Clock and data toggle frequencies A properly designed two-flop synchronizer in modern silicon typically yields an MTBF exceeding the age of the universe.