Thermal Time Constant

The junction temperature follows a first-order exponential response to a step change in power dissipation. After one time constant (τ), the temperature reaches 63.2% of its final steady-state value. After 5τ, the device is considered thermally settled at 99.3% of steady state. This exponential behavior means that low-frequency envelope variations—those with periods comparable to τ—produce the most significant dynamic gain and phase shifts.

A power amplifier does not have a single time constant but a spectrum of time constants corresponding to different physical layers in the heat dissipation path:

• Die-level (nanoseconds to microseconds): Immediate self-heating at the transistor channel
• Die attach and substrate (microseconds to milliseconds): Heat spreading through the semiconductor bulk
• Package and heat sink (milliseconds to seconds): Slow thermal diffusion to the ambient environment

Each stage contributes a distinct pole to the Foster or Cauer thermal model.

The thermal time constant is the product of thermal resistance (Rth) and thermal capacitance (Cth) at a given node in the heat dissipation path:

τ = Rth × Cth

• Rth represents the opposition to heat flow (K/W)
• Cth represents the material's capacity to store heat energy (J/K)

A high-power GaN-on-SiC HEMT might exhibit a junction-to-case time constant of 50–200 µs, while the case-to-ambient path through a heat sink can have time constants exceeding 10 seconds.

The thermal time constant directly dictates the memory span of thermal distortion. Signal envelope components with frequencies below 1/(2πτ) fall within the thermal bandwidth and produce temperature modulation. For a device with τ = 100 µs:

• Envelope frequencies below ~1.6 kHz cause significant junction temperature swing
• This corresponds to modulation bandwidths where thermal AM-AM and AM-PM distortion become non-negligible
• Long-term evolution (LTE) and 5G NR signals with wideband envelopes require predistorters that incorporate thermal memory terms spanning multiple time constants.

Time constants are experimentally extracted using transient thermal response measurements:

1. Apply a known power step to the device under test
2. Monitor a temperature-sensitive electrical parameter (TSEP), such as the forward voltage of a body diode
3. Fit the cooling or heating curve to a multi-exponential model
4. Deconvolve the response to obtain the time-constant spectrum

This structure function analysis reveals discrete Rth-Cth pairs corresponding to each physical layer in the thermal path.

Knowledge of thermal time constants informs thermal-aware DPD design:

• Short τ (< 10 µs): Correctable by conventional memory polynomial terms
• Medium τ (10 µs – 1 ms): Requires dedicated low-frequency memory taps or thermal convolution blocks
• Long τ (> 1 ms): May be addressed through quiescent bias tracking or slow LUT adaptation rather than sample-by-sample correction

Mismatch between the predistorter's memory depth and the actual thermal time constants results in residual spectral regrowth that cannot be eliminated by increasing model order alone.

A lumped-element circuit representing the heat dissipation path from the transistor junction through the die attach, package, and heat sink to ambient. Each material interface contributes a discrete thermal resistance, and the total junction-to-ambient resistance determines steady-state temperature rise per watt of power dissipation. This network forms the backbone of compact electro-thermal models used in predistortion coefficient lookup.

The ability of semiconductor material and packaging to store heat energy, creating the temporal lag that defines thermal memory. When combined with thermal resistance, capacitance produces the RC time constants responsible for slow-memory effects:

• Die-level capacitance: Small, responds in microseconds
• Package-level capacitance: Larger, responds in milliseconds
• Heat sink capacitance: Largest, responds in seconds This hierarchy creates multi-rate thermal dynamics that predistorters must model.

A canonical mathematical representation of thermal impedance using a series of parallel RC ladder stages. Each stage captures a distinct time constant from the device's transient heating curve. Critically, the Foster network provides a behavioral fit without direct physical correspondence to material layers—the R and C values are mathematical constructs, not physical resistances and capacitances. Widely used in compact models because it maps directly to Laplace-domain transfer functions for predistortion algorithms.

A physically-based thermal model representing heat flow through distinct material layers as a ladder network of capacitors connected to ground. Unlike the Foster model, each stage corresponds directly to a physical layer:

• Die → Substrate → Die attach → Package → Heat sink This physical correspondence makes Cauer models ideal for finite element co-simulation and for predicting how changes in packaging or die attach materials affect thermal memory duration.

A behavioral model structure that augments standard memory polynomials with additional terms specifically designed to capture low-frequency, long-duration thermal lag effects. Standard memory polynomials handle electrical memory (nanosecond scale), but thermal memory operates on microsecond-to-millisecond scales. The augmented model adds envelope-dependent terms with long delay taps, enabling a single predistorter to compensate for both fast electrical trapping and slow thermal dynamics simultaneously.

A destructive positive feedback loop where increased junction temperature causes higher leakage current, which further increases power dissipation and temperature until device failure. In GaN and GaAs power amplifiers, this is a critical reliability concern:

• Threshold voltage decreases with temperature
• Subthreshold leakage increases exponentially
• Drain current rises, accelerating self-heating Thermal-aware predistortion must avoid pushing amplifiers into operating regions where runaway becomes possible.