Thermal Impedance

Unlike static thermal resistance (θ_JC), thermal impedance Z_θ(t) captures the time-dependent nature of heat flow. It defines the temperature rise per watt of dissipated power as a function of pulse duration. For short pulses, the thermal capacitance of the die dominates, resulting in low impedance. As pulse width increases, heat penetrates deeper into the package and heatsink, causing impedance to rise until reaching steady-state thermal resistance.

Two equivalent circuit topologies represent thermal impedance:

• Foster Model: A series of parallel RC stages providing a mathematical fit to the transient heating curve. The intermediate nodes have no physical meaning, but the model is simple to extract from curve fitting.
• Cauer Model: A ladder network with capacitors connected to thermal ground. Each RC stage corresponds directly to a physical material layer (die, solder, baseplate), making it ideal for finite element correlation.

Thermal impedance is highly frequency-dependent. The thermal cutoff frequency (typically 1 Hz to 1 kHz for GaN devices) defines the boundary between:

• Low-frequency region: Junction temperature tracks the instantaneous envelope power, causing significant thermal memory effects.
• High-frequency region: Thermal capacitance filters temperature fluctuations, resulting in a quasi-static operating point. This frequency dependence is why wideband signals with high peak-to-average ratios produce complex thermal distortion.

Thermal impedance directly determines the memory depth required in a predistorter:

• Long thermal time constants (milliseconds to seconds) create low-frequency distortion that memoryless DPD cannot correct.
• Thermal-induced AM-AM and AM-PM hysteresis appears as trajectory-dependent gain and phase shifts.
• Effective linearization requires augmenting the DPD model with thermal-aware terms that account for the convolution of signal power with Z_θ(t).

In multi-finger transistors and Doherty amplifiers, thermal impedance is not a single scalar but a matrix of self and mutual impedances:

• Self-heating: Temperature rise in a finger due to its own dissipation.
• Thermal crosstalk: Temperature rise in one finger caused by adjacent finger dissipation. This coupling creates non-uniform temperature distributions across the die, causing individual transistor cells to operate at different bias points and distorting the combined output signal.

A distortion mechanism where the device's temperature history—driven by signal envelope variations—alters instantaneous electrical behavior. Unlike electrical memory effects that decay in nanoseconds, thermal memory persists for microseconds to milliseconds, creating a long-term nonlinear memory that standard memory polynomials struggle to capture. The effect manifests as envelope-dependent gain and phase shifts that vary with the signal's recent power history.

The process by which power dissipation within a transistor channel increases its own junction temperature, creating a dynamic feedback loop. Key mechanisms:

• Increased channel temperature reduces carrier mobility
• Threshold voltage shifts with temperature
• Gain compression and phase rotation become power-history dependent
• In GaN HEMTs, self-heating interacts with trapping effects to create compound memory behaviors

The operating temperature at the semiconductor die level of a transistor, which critically governs:

• Carrier mobility and saturation velocity
• Threshold voltage (Vth) through temperature-dependent Fermi potential
• Leakage currents that shift the quiescent bias point
• Instantaneous nonlinear characteristics including gain, phase, and efficiency

Accurate junction temperature estimation is essential for thermal-aware predistortion algorithms.

The characteristic time required for a device's junction temperature to reach approximately 63.2% of its steady-state value following a step change in power dissipation. This parameter:

• Dictates the memory duration of thermal effects
• Varies across device layers (die, attach, package, heatsink)
• Creates a multi-time-constant response requiring Foster or Cauer network modeling
• Determines the bandwidth over which thermal memory compensation must operate

A co-simulation technique that couples semiconductor device physics with dynamic heat generation and dissipation equations. The approach:

• Solves the heat equation alongside device transport equations
• Predicts temperature-dependent electrical nonlinearities in real time
• Enables extraction of thermal impedance parameters for compact models
• Provides the foundation for thermal-aware digital predistortion algorithms that compensate for dynamically shifting amplifier characteristics

Two canonical representations of thermal impedance:

Foster Network: Series-connected parallel RC stages providing a behavioral fit to transient heating curves. Mathematically convenient but lacks direct physical correspondence to material layers.

Cauer Network: A ladder of capacitors to ground representing heat flow through distinct material layers. Each stage directly correlates to the thermal resistance and capacitance of a physical layer (die, attach, package, heatsink).

Both are used in thermal convolution predistortion algorithms.