Xilinx RFSoC

The RFSoC integrates high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) capable of direct sampling at multi-gigasample-per-second rates. This eliminates the need for external intermediate frequency (IF) stages and analog mixers in the DPD observation path.

• Directly digitizes RF signals up to C-band without external downconverters
• Reduces component count, board space, and system cost
• Simplifies the feedback path architecture for wideband DPD applications

By embedding data converters on the same silicon die as the FPGA fabric, the RFSoC removes the JESD204B serial interface bottleneck between converters and processing logic. This architectural decision has profound implications for DPD latency.

• Eliminates serializer/deserializer (SERDES) latency in the feedback loop
• Removes complex multi-lane synchronization and deterministic latency management
• Enables sub-microsecond round-trip DPD loop delays critical for wideband signals

The RFSoC includes hardened LDPC and Turbo codec blocks for 5G wireless applications. While primarily for channel coding, these blocks can be co-opted for DPD coefficient reliability processing.

• Provides dedicated, low-power error correction without consuming FPGA logic
• Supports 5G NR LDPC decoding for integrated radio and DPD solutions
• Frees programmable logic resources for custom predistorter cores

The RFSoC architecture supports deterministic multi-tile synchronization across multiple converter blocks using a shared reference clock and synchronization signals. This is essential for massive MIMO and multi-antenna DPD systems.

• Enables sample-accurate alignment across 16+ transmit and receive channels
• Supports beamforming-aware DPD with phase-coherent correction
• Simplifies time alignment in multi-branch observation receivers

RFSoC devices combine the programmable logic with a quad-core ARM Cortex-A53 processing system and dual-core ARM Cortex-R5 real-time processors. This heterogeneous architecture enables optimal DPD functional partitioning.

• Hard real-time processors handle adaptive coefficient estimation algorithms
• ARM application processors run Linux-based DPD management and monitoring
• FPGA fabric implements the high-speed predistorter core and data pipelines

Integrated digital step attenuators (DSAs) and digital down/up converters (DDCs/DUCs) within the RFSoC's converter tiles provide on-chip signal conditioning essential for DPD feedback path optimization.

• Built-in DDCs reduce sample rates before FPGA processing, saving logic resources
• Integrated DSAs enable automatic gain control in the observation receiver
• Fractional decimation and interpolation support flexible DPD bandwidth scaling

The primary data transport protocol within the RFSoC fabric for DPD signal chains. This unidirectional, point-to-point protocol from the ARM AMBA 4 specification connects the predistorter core directly to the integrated DACs without buffering overhead. Key characteristics:

• Uses a simple TVALID/TREADY handshake for backpressure
• Supports continuous streaming of complex baseband samples
• Eliminates the need for address-based memory-mapped transactions in the forward path
• Enables direct connection between HLS-generated DPD IP and the RF data converter tiles

The high-speed serial interface standard that the RFSoC architecture eliminates from the DPD feedback path. In traditional architectures, JESD204B provides deterministic latency and high lane density for connecting discrete ADCs and DACs to the FPGA. The RFSoC's direct integration of data converters bypasses this entirely:

• Removes JESD204B IP core resource consumption
• Eliminates SERDES power dissipation in the feedback loop
• Reduces the DPD observation path latency by avoiding serialization/deserialization stages
• Simplifies board design by removing high-speed differential routing constraints

The observation receiver chain that captures a coupled sample of the power amplifier output for predistorter training. On the RFSoC, this path is dramatically simplified:

• The integrated RF-ADC directly digitizes the downconverted feedback signal
• Multi-gigasample sampling rates enable wideband linearization without analog bandwidth constraints
• The digitized samples stream directly into the FPGA fabric via AXI4-Stream for time alignment with the transmitted reference
• Eliminates external ADC packaging, power supplies, and clock distribution complexity

Serializer/deserializer transceiver blocks that form the physical layer for JESD204B links to external data converters. The RFSoC's architectural innovation removes SERDES from the DPD data path entirely. Impact on DPD implementation:

• Eliminates the multi-gigabit transceiver power budget from the linearization subsystem
• Removes a source of non-deterministic latency in the feedback loop
• Frees high-speed transceiver quads for other system interfaces
• Simplifies clock domain crossing management between the converter sample clock and the FPGA fabric clock

A critical signal processing step that synchronizes the transmitted reference signal with the received feedback signal before model extraction. The RFSoC's integrated architecture simplifies alignment:

• The deterministic latency between DAC output and ADC input is known and repeatable
• No external cabling or board trace length matching introduces unknown delays
• Fractional delay filters can achieve sub-sample alignment precision
• Correlation-based alignment algorithms converge faster due to reduced jitter in the observation path
• Essential for accurate indirect learning architecture coefficient estimation

The process of changing the sampling rate of a discrete signal, often required in the DPD feedback path to align the observation receiver bandwidth with the predistorter processing rate. The RFSoC's integrated converters operate at multi-gigasample rates, enabling:

• Direct sampling at 5 GSPS or higher for wideband signal capture
• Fractional decimation within the RF data converter tile to match the FPGA fabric clock rate
• Polyphase filter implementations in the FPGA logic for arbitrary rate changes
• Avoidance of external analog bandwidth limitations that would require complex digital up/down conversion chains