Volterra Kernel

A Volterra kernel is a multidimensional impulse response that characterizes a specific order of nonlinearity and memory depth. The first-order kernel h₁(τ₁) is the standard linear impulse response. The second-order kernel h₂(τ₁, τ₂) describes quadratic nonlinear interactions between two delayed input samples. The nth-order kernel hₙ(τ₁, …, τₙ) captures nth-order nonlinearity with n-dimensional memory. Each kernel dimension corresponds to a time delay variable, making the representation complete but computationally intensive.

Volterra kernels exhibit permutation symmetry without loss of generality. For an nth-order kernel, the value hₙ(τ₁, τ₂, …, τₙ) is identical for any permutation of its delay arguments. This symmetry arises because the kernel multiplies input samples that are commutative in the Volterra series expansion. Exploiting this property reduces the number of unique coefficients by a factor of n!, significantly decreasing storage requirements and computational complexity in hardware implementations.

By enforcing symmetry, the nth-order kernel can be represented in a triangular domain where τ₁ ≥ τ₂ ≥ … ≥ τₙ. This reduces the coefficient count from Mⁿ to approximately Mⁿ/n! for a memory depth M. For example, a third-order kernel with M=5 requires only 35 unique coefficients instead of 125. This triangular structure is essential for practical FPGA implementations where memory and multiplier resources are constrained.

Kernel coefficients are classified by their delay relationships:

• Diagonal terms: All delays equal (τ₁ = τ₂ = … = τₙ). These capture static nonlinearity without memory effects.
• Off-diagonal terms: Delays differ. These capture dynamic nonlinear memory effects where past inputs interact nonlinearly. The memory polynomial model simplifies the Volterra series by retaining only diagonal terms, trading modeling accuracy for dramatic computational savings. Full Volterra kernels include both diagonal and off-diagonal contributions for maximum fidelity.

Each kernel is defined by two parameters:

• Order (n): The degree of nonlinearity. Odd-order kernels (3rd, 5th, 7th) dominate in differential PA architectures, while even-order kernels are critical for single-ended designs.
• Memory depth (M): The number of past samples considered. Longer memory captures low-frequency thermal and bias circuit effects. Typical DPD implementations truncate at 5th or 7th order with memory depths of 3-5 samples, balancing linearization performance against FPGA resource utilization.

Not all kernel coefficients contribute equally to linearization. Coefficient pruning techniques identify and eliminate near-zero terms:

• Magnitude thresholding: Remove coefficients below a specified amplitude.
• Perturbation analysis: Assess each coefficient's impact on ACLR improvement.
• LASSO regularization: Enforce sparsity during model extraction. Pruning can reduce coefficient count by 60-80% with minimal linearization degradation, enabling real-time DPD on resource-constrained FPGAs.

A memory polynomial is a simplified subset of the Volterra series that retains only the diagonal terms of the kernels. This dramatically reduces the number of coefficients while still capturing both static nonlinearity and memory effects. It is the most widely adopted behavioral model for DPD because it offers an excellent trade-off between linearization accuracy and FPGA implementation complexity.

The Generalized Memory Polynomial extends the memory polynomial by adding cross-terms between the signal and its lagging or leading envelope values. This captures more complex nonlinear memory interactions, such as those caused by bias network modulation and thermal trapping in GaN amplifiers, while remaining more tractable than a full Volterra series.

Kernel truncation is the practical necessity of limiting the Volterra series to a finite nonlinear order and memory depth. A 3rd-order, 3-tap model might suffice for a narrowband Class-AB amplifier, while a 7th-order, 5-tap model may be required for a wideband Doherty PA. Truncation directly determines the coefficient count and the hardware resources consumed in an FPGA predistorter core.

These are block-structured simplifications of the Volterra series. A Hammerstein model cascades a static nonlinearity followed by a linear filter, while a Wiener model reverses the order. They are computationally efficient but cannot represent the full interaction between nonlinearity and memory. They serve as useful baselines for evaluating more complex DPD structures.

Volterra kernel coefficients are typically estimated using least squares (LS) estimation in the indirect or direct learning architecture. The predistorter output is formulated as a linear regression problem: y = X * w, where X is the regressor matrix of basis waveforms and w is the vector of kernel coefficients. The solution w = (X^H X)^{-1} X^H y is computed using QR decomposition or Cholesky factorization for numerical stability.