SERDES

The core function of a SERDES transmitter is to serialize a wide parallel data bus into a single high-speed differential lane. Serializer logic takes an N-bit word from the FPGA fabric at a lower frequency and shifts it out at N times that rate.

• Data Widths: Common ratios include 8:1, 16:1, 32:1, and 40:1.
• Gearbox Logic: Advanced blocks handle 64B/66B or 8B/10B encoding to ensure DC balance and sufficient transition density for clock recovery.
• Example: A 32-bit bus running at 312.5 MHz is serialized into a single lane running at 10 Gbps.

The receiver extracts a clock directly from the incoming serial data stream, eliminating the need for a separate forwarded clock. A Phase-Locked Loop (PLL) or Phase Interpolator (PI)-based CDR locks to the transitions in the data.

• Baud-Rate CDR: Samples directly at the center of the data eye, offering superior power efficiency at high rates.
• Oversampling CDR: Uses multiple phases to sample the eye, providing robust jitter tolerance.
• Critical Metric: CDR lock time and jitter tolerance (expressed in Unit Intervals, UI) directly impact link reliability.

To combat inter-symbol interference (ISI) caused by skin effect and dielectric loss in the PCB channel, SERDES transceivers employ signal conditioning. The transmitter uses Finite Impulse Response (FIR) pre-emphasis to boost high-frequency components, while the receiver applies Continuous Time Linear Equalization (CTLE) and Decision Feedback Equalization (DFE).

• Pre-Emphasis: Adjustable tap weights (pre-cursor, main, post-cursor) shape the transmitted eye.
• CTLE: A linear amplifier that boosts the Nyquist frequency to open the closed eye.
• DFE: A non-linear feedback loop that subtracts ISI from previously decided bits without amplifying noise.

The SERDES is architecturally divided into the Physical Medium Attachment (PMA) and the Physical Coding Sublayer (PCS). The PMA contains the analog front-end—serializers, deserializers, CDR, and drivers—while the PCS handles digital logic like encoding, scrambling, and lane bonding.

• PMA Layer: Responsible for raw bit-level transmission and eye diagram integrity.
• PCS Layer: Implements 8B/10B or 64B/66B encoding, elastic buffers for clock domain crossing, and lane alignment for multi-lane links.
• DPD Relevance: The deterministic latency of JESD204B is enforced by the PCS layer's SYNC and SYSREF handshaking, ensuring the feedback sample aligns with the transmitted reference.

For wideband DPD observation paths requiring multiple converter lanes, SERDES channels must be bonded to act as a single logical link. Lane bonding compensates for PCB trace length mismatches and process variations.

• Training Sequence: JESD204B uses an Initial Lane Alignment Sequence (ILAS) during link establishment to deskew lanes at the receiver.
• Elastic Buffer: Absorbs residual skew between lanes after alignment, typically measured in Unit Intervals.
• Example: A 4-lane JESD204B link at 10 Gbps provides 40 Gbps of aggregate bandwidth for a dual-channel 5 GSPS ADC feedback path.

The eye diagram is the universal visualization of SERDES signal integrity, formed by overlaying millions of unit intervals. A wide, open eye indicates low jitter and ISI, ensuring a low Bit Error Rate (BER).

• Eye Height: Vertical opening indicating noise margin; degraded by power supply ripple.
• Eye Width: Horizontal opening indicating timing margin; degraded by jitter and ISI.
• Target BER: DPD feedback paths typically require a BER better than 10^-12 to avoid coefficient corruption.
• Built-in Test: Modern transceivers include IBERT (Integrated Bit Error Ratio Tester) cores for in-system eye scan and margin analysis.

The passage of signals between two asynchronous clock domains on an FPGA. In DPD systems, the SERDES operates at the line rate clock while the predistorter core runs at the baseband sample clock. Improper CDC handling causes metastability—unpredictable flip-flop states that corrupt data. Mitigation techniques include:

• Double-flop synchronizers for single-bit signals
• Asynchronous FIFOs with Gray-coded pointers for multi-bit buses
• Recirculation muxes for deterministic latency paths

The process of changing the sampling rate of a discrete signal, often required in the DPD feedback path to align the observation receiver bandwidth with the predistorter processing rate. The SERDES delivers samples at the converter's native rate, but the DPD engine may operate at a different rate. Common SRC techniques include:

• Polyphase interpolation for integer ratio changes
• Farrow structures for arbitrary fractional resampling
• CIC filters for high-rate decimation with minimal multiplier usage Fractional SRC is particularly critical when the feedback ADC samples at a non-integer multiple of the baseband symbol rate.

A critical signal processing step that precisely synchronizes the transmitted reference signal with the received feedback signal before model extraction. The SERDES introduces fixed pipeline latency, but additional misalignment arises from:

• Analog group delay in the PA and coupler
• Cable length differences in test setups
• Buffer fill levels in asynchronous FIFOs Alignment is typically performed using cross-correlation between the reference and feedback waveforms, achieving sub-sample precision through Lagrange interpolation. Without accurate time alignment, the DPD model will attempt to correct non-existent distortion, degrading rather than improving linearity.

A high-throughput, unidirectional point-to-point protocol from the ARM AMBA 4 specification. In FPGA DPD designs, the SERDES output typically connects to the predistorter core via AXI4-Stream, providing:

• Backpressure through the TVALID/TREADY handshake
• Packet delineation via the TLAST signal for frame-based processing
• Sideband signaling through TUSER for metadata like overflow flags The streaming model maps naturally to the continuous-flow nature of DPD signal processing, avoiding the address overhead and arbitration latency of memory-mapped AXI4 interfaces.