Sample Rate Conversion (SRC)

Unlike simple integer-ratio decimation, FPGA-based DPD systems require arbitrary rational resampling to align the observation receiver's fixed ADC clock with the transmitter's baseband rate. This is typically implemented using a Farrow structure or a polyphase filter bank that computes fractional interpolation and decimation factors on the fly. The resampling ratio is often an irrational number derived from non-coherent clock sources, demanding high-precision phase accumulator arithmetic to prevent long-term timing drift between the reference and feedback signals.

The SRC block must preserve absolute phase coherence between the transmitted reference waveform and the resampled feedback signal. Any phase discontinuity introduced by the resampling filter destroys the alignment required for memory polynomial model extraction. This is achieved through linear-phase FIR filter designs with symmetric coefficient sets. The group delay through the SRC must be constant and known to the sample, allowing the time alignment block to apply a static integer delay correction without residual fractional skew.

During interpolation, the SRC introduces spectral images at multiples of the input sample rate. These images must be suppressed below the DPD observation path's noise floor to prevent aliasing into the band of interest during subsequent decimation. The anti-imaging filter is integrated into the polyphase decomposition of the resampler, with stop-band attenuation typically exceeding -80 dBc. Insufficient rejection causes the coefficient estimation algorithm to model the SRC's artifacts rather than the power amplifier's true nonlinear behavior.

The SRC's processing latency is not static; it varies fractionally with the instantaneous resampling ratio. The DPD system must account for this dynamic group delay in its time alignment loop. A common approach pairs the SRC with a FIFO-based delay compensation buffer that absorbs the variable latency. The buffer's read pointer is controlled by the same phase accumulator that drives the resampler, ensuring that the output sample stream maintains a fixed temporal relationship with the system's master timing reference.

The SRC's internal arithmetic word length directly sets the noise floor of the resampled signal. Insufficient bit width in the phase accumulator causes spurious phase modulation, which manifests as jitter sidebands on the feedback signal. Similarly, coefficient quantization in the polyphase filter introduces a stationary error floor. For wideband 5G signals with high peak-to-average power ratios, SRC implementations typically require 18-bit to 24-bit data paths and 32-bit phase accumulators to keep quantization artifacts below the power amplifier's residual distortion level after linearization.

To meet the multi-gigasample per second throughput demands of wideband DPD, the SRC is decomposed into a polyphase architecture. The interpolation filter is partitioned into N parallel sub-filters, each operating at 1/N of the output sample rate. This allows the FPGA's DSP48 slices to be time-shared efficiently, with each slice computing a partial output sample per clock cycle. The polyphase structure naturally maps to the parallel data paths of JESD204B interfaces, enabling seamless integration with high-speed ADCs without requiring a serial-to-parallel conversion bottleneck.

The process of reducing the sampling rate of a signal by an integer factor M. In the DPD feedback path, decimation is used to bring the high-speed ADC output down to the processing rate of the predistorter. It requires an anti-aliasing filter before downsampling to prevent spectral folding. For example, decimating a 491.52 MSPS observation signal by 2 yields 245.76 MSPS, matching a common baseband processing rate.

The process of increasing the sampling rate by an integer factor L. Interpolation inserts zeros between original samples and applies a low-pass filter to remove spectral images. In DPD, interpolation may be needed to match the predistorter output rate to a higher DAC sampling rate, ensuring the correction signal has sufficient bandwidth to cover distortion products beyond the original signal bandwidth.

A combined decimation and interpolation operation that changes the sampling rate by a rational factor L/M. This is essential when the ADC and baseband clocks are derived from different reference oscillators. A common implementation uses a polyphase filter bank to efficiently perform interpolation by L followed by decimation by M in a single stage, minimizing computational load.

A computationally efficient structure for implementing multirate filters. By decomposing a prototype FIR filter into M polyphase sub-filters, the filtering and downsampling operations can be reordered so that only the retained output samples are computed. This reduces the required multiply-accumulate operations by a factor of M, critical for meeting real-time latency budgets in FPGA-based DPD.

A Cascaded Integrator-Comb filter is a multiplierless structure ideal for high-rate decimation or interpolation. Its transfer function uses only adders and registers, making it extremely resource-efficient in FPGAs. CIC filters are often used as the first stage of a multi-stage SRC chain to reduce the rate before a compensating FIR filter corrects the passband droop. Commonly found in Xilinx RFSoC DDC chains.

The JESD204B standard provides mechanisms for deterministic latency across the serial link between ADC and FPGA. This is critical for SRC in DPD because the time alignment between the transmitted reference and the feedback signal must be known with sample-level precision. Subclass 1 uses an external SYSREF signal to achieve deterministic phase alignment across multiple converter lanes.