Memory Polynomial

The memory polynomial structure treats nonlinearity and memory as separable operations, applying a polynomial to the current and delayed input samples independently. This contrasts with the full Volterra series, where cross-terms between different delays create a combinatorial explosion of coefficients. The model is defined as a sum of polynomials applied to delayed envelope samples, making it a pruned subset of the Volterra series that retains only the diagonal kernel terms.

Compared to the generalized memory polynomial (GMP) or full Volterra series, the standard memory polynomial offers a linear scaling of coefficients with memory depth and nonlinearity order. For a model with nonlinearity order K and memory depth M, the number of complex coefficients is approximately K × (M+1), avoiding the exponential growth of cross-terms. This makes it the preferred structure for resource-constrained FPGA implementations where multiplier count and DSP48 slice utilization are critical design parameters.

The memory polynomial operates on the complex baseband envelope of the signal, modeling the bandpass nonlinearity around the carrier frequency. The output at time n is expressed as:

• A sum over memory taps m and odd-order nonlinearity terms k
• Each term multiplies the delayed input sample by a complex coefficient and a power of the envelope magnitude
• Only odd-order terms are retained, as even-order distortion products fall outside the band of interest in a properly filtered transmitter

The memory polynomial is linear in its parameters, enabling coefficient extraction using standard least-squares estimation. By constructing a regression matrix from the delayed and exponentiated input samples, the optimal predistorter or PA model coefficients can be solved in a single step. This linear-in-parameters property is a key advantage over neural network-based DPD, which requires iterative gradient-based training and may converge to local minima.

The standard memory polynomial cannot capture cross-terms between different delay taps, which limits its accuracy for power amplifiers exhibiting strong long-term memory effects such as thermal trapping in GaN HEMT devices or bias network modulation. In these cases, the model's linearization performance degrades, and more expressive structures like the generalized memory polynomial (GMP) or augmented Hammerstein models become necessary to achieve the required adjacent channel leakage ratio (ACLR) targets.

The memory polynomial maps directly to a tapped delay line followed by parallel polynomial evaluation paths, a structure that is highly amenable to FPGA implementation. Key implementation considerations include:

• Coefficient quantization from floating-point to fixed-point representation
• Pipelining of complex multipliers to meet timing closure at high sample rates
• Exploiting symmetry in odd-order terms to reduce the number of required multipliers
• Using time-division multiplexing of a single polynomial evaluation unit across multiple memory taps to trade throughput for resource usage

The most general mathematical descriptor of a nonlinear dynamic system. A Volterra kernel is a multidimensional impulse response that characterizes a specific order of nonlinearity and memory depth. The memory polynomial is a drastic simplification of the full Volterra series, achieved by retaining only the diagonal terms of the kernels. While the full Volterra model captures complex cross-terms between different time delays, its computational complexity grows exponentially with memory depth, making it impractical for real-time FPGA implementation.

An extension of the standard memory polynomial that reintroduces select cross-terms between delayed envelope samples to capture more complex memory effects. The GMP adds two additional summations: one for lagging cross-terms (envelope at time n multiplied by signal at time n-m) and one for leading cross-terms (signal at time n multiplied by envelope at time n-m). This structure bridges the gap between the computational simplicity of the memory polynomial and the modeling accuracy of the full Volterra series, making it a popular choice for wideband Doherty amplifier linearization.

A numerical representation system where digits have a fixed radix point, essential for implementing memory polynomial DPD on FPGAs. Unlike floating-point, fixed-point arithmetic uses integer hardware multipliers and adders, dramatically reducing DSP48 slice consumption. Key design decisions include:

• Word length (Q-format): Typically Q16.16 for coefficients, balancing precision against resource usage
• Saturation vs. wrap-around: Overflow handling strategy for accumulated multiply-add operations
• Rounding modes: Truncation versus convergent rounding to minimize quantization noise in the feedback path

The dominant coefficient extraction topology used with memory polynomial predistorters. In an ILA, a post-distorter model is trained on the power amplifier's output and then copied directly to the predistorter. This elegant approach avoids the need to assume a specific PA model during identification. For a memory polynomial, the ILA training solves a least-squares problem where the coefficient vector is estimated from a matrix of delayed envelope terms. The key advantage: the post-distorter sees the same signal statistics as the predistorter, ensuring robust convergence.

The process of converting high-precision memory polynomial coefficients from a floating-point training algorithm into a fixed-point representation for FPGA implementation. Coefficient quantization involves a fundamental trade-off:

• More bits: Higher linearization accuracy, lower EVM, but increased DSP slice and BRAM consumption
• Fewer bits: Compact hardware footprint, but risk of spectral regrowth due to coefficient rounding errors Typical implementations use 16- to 18-bit coefficients, with sensitivity analysis revealing that higher-order polynomial terms tolerate more aggressive quantization than linear terms.

A dedicated high-speed arithmetic logic block within Xilinx FPGAs, optimized for the multiply-accumulate (MAC) operations at the heart of memory polynomial evaluation. Each DSP48 slice contains:

• A 25×18-bit signed multiplier
• A 48-bit accumulator with cascade paths
• Optional pre-adder for symmetric filter structures A memory polynomial predistorter maps naturally to a pipeline of DSP48 slices, where each slice computes one polynomial term's contribution to the complex gain correction. Resource estimation: a memory polynomial with nonlinearity order K=7 and memory depth M=3 requires approximately 21 complex multipliers, each consuming 3-4 DSP48 slices.