Look-Up Table (LUT) DPD

The LUT is addressed by the instantaneous magnitude of the complex baseband input signal. An address generation unit computes |x(n)|, which serves as the index into a table of pre-computed complex gain values. This one-to-one mapping between input envelope and correction factor eliminates the need for real-time polynomial evaluation, reducing multiply-accumulate operations to a single complex multiplication per sample.

Basic LUT DPD corrects only static nonlinearity. To address PA memory effects, the architecture extends to multi-dimensional LUTs indexed by both current magnitude and delayed magnitude samples. A 2D LUT addressed by |x(n)| and |x(n-1)| captures first-order memory, while higher dimensions model longer memory spans. The trade-off is exponential table growth: a 256-entry 1D LUT becomes 65,536 entries in 2D.

LUT coefficients are updated using the Indirect Learning Architecture. A post-distorter LUT is trained on the PA output, then the entire table is copied to the predistorter. Adaptation algorithms include:

• Linear interpolation: Smooths between discrete LUT entries to reduce quantization error
• Least Mean Squares (LMS): Iteratively updates individual table entries based on the error between desired and actual PA output
• Secant method: Rapidly converges on optimal complex gain values for each table index

LUT DPD shifts the resource burden from DSP slices to Block RAM (BRAM). A 256-entry complex LUT consumes one BRAM36 primitive on Xilinx devices, compared to dozens of DSP48 slices for an equivalent polynomial DPD. This makes LUT DPD ideal for:

• Cost-optimized FPGA families with limited DSP resources
• Multi-antenna systems where per-chain DSP multiplication would exceed device capacity
• Applications where BRAM is abundant but DSP count is the binding constraint

Finite LUT depth introduces quantization distortion when the input magnitude falls between table entries. Mitigation strategies include:

• Linear interpolation: Computes a weighted average of the two nearest entries, requiring one additional multiply and add
• Higher-order interpolation: Quadratic or cubic spline interpolation for smoother correction at the cost of more DSP resources
• Oversized tables: Simply increasing LUT depth to 512 or 1024 entries reduces quantization error without interpolation logic, trading BRAM for simplicity

The process of mapping high-precision complex gain values into a finite set of discrete levels stored in the LUT. Bit-width selection directly governs the trade-off between correction accuracy and BRAM resource consumption. A 16-bit quantized LUT may achieve -55 dBc ACLR, while an 8-bit table limits performance to -45 dBc. Key considerations include:

• Uniform quantization: Equal step sizes across the magnitude range, simplest to implement
• Non-uniform quantization: Finer steps in the compression region where the PA nonlinearity changes most rapidly
• Overflow handling: Saturation logic to prevent wraparound distortion at the table boundaries

A closed-loop architecture that continuously updates LUT entries in real-time to track time-varying PA nonlinearity caused by temperature drift, supply voltage sag, and device aging. Unlike static LUT DPD, adaptive systems employ a dedicated observation receiver and coefficient update engine. Common adaptation strategies include:

• Least Mean Squares (LMS): Simple, low-complexity iterative update suitable for direct table entry adjustment
• Recursive Least Squares (RLS): Faster convergence at the cost of higher computational complexity
• Batched updates: Accumulating error statistics over multiple samples before modifying the LUT to reduce update noise

A behavioral model structure that captures both static nonlinearity and memory effects by including delayed envelope terms. While LUT DPD excels at static AM-AM and AM-PM correction, memory polynomial models address dynamic distortion. A hybrid approach often combines:

• LUT for static predistortion: Fast, low-latency correction indexed by instantaneous magnitude
• FIR filter for memory compensation: A short tapped-delay line that corrects frequency-dependent nonlinearity
• Generalized Memory Polynomial (GMP): Extends the structure with cross-terms between current and lagging envelope values for improved wideband performance

The numerical representation system essential for efficient LUT DPD implementation on FPGAs without the prohibitive resource cost of floating-point units. Q-format notation specifies the number of integer and fractional bits. Critical design decisions include:

• Magnitude indexing precision: The number of fractional bits in the envelope calculation determines how finely the LUT address resolves the input signal
• Gain value representation: Complex correction factors stored as (I, Q) pairs with carefully chosen radix points
• Rounding modes: Truncation versus convergent rounding and their impact on EVM floor
• Guard bits: Extra bits maintained during accumulation to prevent overflow in the complex multiplier output

A signal conditioning stage applied before the LUT predistorter to reduce the peak-to-average power ratio (PAPR) of the transmission waveform. CFR prevents the input signal from driving the PA into deep saturation where even an ideal LUT cannot linearize the output. Common techniques include:

• Peak windowing: Multiplying signal peaks with a smooth window function to limit spectral regrowth
• Clipping and filtering: Hard amplitude limiting followed by bandpass filtering to remove out-of-band distortion products
• Pulse injection: Adding cancellation pulses at detected peak locations CFR and LUT DPD work synergistically: CFR handles extreme peaks while the LUT corrects moderate nonlinearity in the PA's operating range.

A critical preprocessing step in the DPD feedback path that precisely synchronizes the transmitted reference signal with the observed PA output before LUT adaptation. Sub-sample alignment accuracy is mandatory for correct table entry updates. Implementation approaches include:

• Cross-correlation: Finding the integer sample delay by locating the peak of the correlation function
• Fractional delay filters: Farrow structure or Lagrange interpolation to achieve sub-sample alignment
• Hardware correlation accelerators: Dedicated DSP blocks that compute correlation in real-time without burdening the processor Misalignment by even 0.1 samples can degrade ACLR improvement by several dB, making this step non-negotiable for adaptive LUT DPD systems.