Peaking Amplifier

The peaking amplifier is biased deeply in Class-C mode, with the gate voltage set significantly below the transistor's pinch-off or threshold voltage. This means the device is in a non-conducting, cut-off state for the majority of the signal cycle.

• Conduction Angle: Less than 180 degrees, typically around 90-120 degrees.
• Quiescent Current: Effectively zero DC current draw when no RF signal is present.
• Efficiency: Extremely high theoretical efficiency, approaching 100% at peak conduction, as current is only drawn during the signal envelope's maxima.
• Trade-off: This deep bias creates severe AM-AM and AM-PM distortion at turn-on, which is the primary non-linearity that digital predistortion must correct.

Unlike the always-active carrier amplifier, the peaking amplifier operates as a modulated current source that only activates when the instantaneous input signal envelope exceeds a predetermined transition point.

• Threshold Activation: The peaking amplifier remains off below the transition point, presenting a high output impedance to the Doherty combiner.
• Current Injection: Once the envelope crosses the threshold, the peaking amplifier begins to source current, actively modulating the load impedance seen by the carrier amplifier.
• Soft Turn-On: In real-world GaN or LDMOS devices, the transition from cut-off to conduction is a gradual, non-ideal process, contributing to soft compression and complex memory effects.
• Phase Step: The activation introduces a sudden phase discontinuity that must be tracked and corrected by the DPD system.

The peaking amplifier's primary function is to perform active load-pull on the carrier amplifier. By injecting current into the common Doherty combiner node, it dynamically transforms the impedance seen by the carrier.

• Low Power: With the peaking amplifier off, the carrier sees a high impedance (e.g., 2*Ropt), allowing it to reach voltage saturation early and achieve peak efficiency at back-off.
• High Power: As the peaking amplifier turns on and contributes current, the impedance seen by the carrier is modulated downward toward its optimal load (Ropt) for maximum power delivery.
• Current Ratio: Ideal load modulation requires a specific, frequency-dependent current ratio between the peaking and carrier amplifiers at peak power.
• Combiner Role: The impedance inverter (quarter-wave transformer) in the combiner is essential for translating the peaking amplifier's current into the correct impedance transformation.

In an Asymmetric Doherty configuration, the peaking amplifier is designed with a larger transistor periphery and higher saturated power capability (e.g., a 2:1 or 3:2 power ratio) compared to the carrier amplifier.

• Extended Range: This allows the peaking amplifier to supply more current, extending the high-efficiency back-off range beyond the standard 6 dB to 8-10 dB or more.
• Higher PAPR Signals: Asymmetric designs are critical for modern 5G signals with peak-to-average power ratios (PAPR) exceeding 9 dB.
• Complex Linearity: The larger peaking device introduces a more severe gain mismatch and a sharper, more nonlinear turn-on characteristic, significantly increasing the linearization burden on the DPD engine.
• Phase Mismatch: The asymmetric periphery requires meticulous input phase alignment to ensure the larger peaking device's output combines constructively with the carrier.

The peaking amplifier is a dominant source of low-frequency memory effects in the Doherty transmitter, which manifest as dynamic, history-dependent distortion.

• Self-Heating: The peaking amplifier's deep Class-C bias means it transitions from a cold, off-state to high instantaneous power dissipation, causing rapid channel temperature fluctuations and transient gain/phase shifts.
• Trap Effects: In GaN HEMT devices, the abrupt turn-on can excite charge trapping and de-trapping phenomena with time constants in the microsecond to millisecond range, creating complex low-frequency dispersion.
• Bias Network Interaction: The sudden current draw interacts with the finite impedance of the DC bias feed network, causing an envelope-dependent voltage sag that modulates the amplifier's operating point.
• DPD Complexity: These long-term thermal and electrical memory effects require DPD models with deep memory taps, such as Generalized Memory Polynomials, to achieve sufficient linearization.

For the Doherty combiner to sum the outputs constructively, the peaking amplifier's output must arrive in-phase with the carrier amplifier's output at the combining node. This requires precise electrical path length matching.

• Input Splitter: A phase shifter or asymmetric power divider at the input compensates for the different phase delays through the carrier and peaking branches.
• Gain Mismatch: The peaking amplifier's Class-C bias gives it lower gain than the Class-AB carrier. The input drive must be adjusted to ensure the correct current ratio is achieved at peak power.
• Frequency Sensitivity: The quarter-wave impedance inverter and phase alignment networks are inherently narrowband, making phase alignment a critical challenge in Broadband Doherty designs.
• AM-PM Profile: The peaking amplifier's phase response is highly nonlinear with drive level, creating a steep AM-PM curve that the DPD must linearize to meet Error Vector Magnitude (EVM) specifications.