Load Modulation

Load modulation is fundamentally an active load-pull effect. As the peaking amplifier transitions from cutoff to conduction, its injected current into the Doherty combiner node dynamically alters the impedance presented to the carrier amplifier's output.

• At low power (back-off), the peaking amplifier is off, presenting a high impedance. The carrier sees an optimal high-impedance load for maximum efficiency.
• At peak power, both amplifiers contribute equally, and the carrier sees a lower impedance matched for maximum saturated power delivery.
• This continuous impedance transformation is governed by the quarter-wave impedance inverter in the output combiner network.

The primary purpose of load modulation is to maintain high Power-Added Efficiency (PAE) when the amplifier operates far below its saturated peak power. Without load modulation, a conventional Class-AB amplifier's efficiency drops linearly with output power.

• A Doherty amplifier achieves a first efficiency peak at the 6 dB back-off point (when the peaking amplifier activates) and a second peak at full saturation.
• This dual-peak efficiency profile is critical for amplifying modern communication signals with high Peak-to-Average Power Ratios (PAPR) , such as OFDM waveforms used in 5G and Wi-Fi.
• The back-off efficiency improvement directly translates to reduced thermal dissipation and lower operating costs for base station infrastructure.

The impedance seen by the carrier amplifier (Z_carrier) is a direct function of the ratio of the peaking amplifier's output current (I_peaking) to the carrier amplifier's output current (I_carrier).

• Low Power Region: I_peaking ≈ 0, so Z_carrier = Z_opt_high (e.g., 100Ω for a 50Ω system).
• Peak Power Region: I_peaking = I_carrier, so Z_carrier = Z_opt_low (e.g., 50Ω).
• This relationship is mathematically described by the impedance inverter equation: Z_carrier = (Z_combiner²) / Z_load, where Z_combiner is the characteristic impedance of the quarter-wave transformer.
• Precise control of the peaking amplifier's gate bias and turn-on characteristics is essential to achieve the correct current profile for smooth impedance modulation.

For load modulation to function correctly, the output currents from the carrier and peaking amplifiers must combine in-phase at the Doherty combiner node. Any phase misalignment degrades the active load-pull effect.

• A phase offset line is typically added to the peaking amplifier's output path to compensate for the phase shift introduced by the impedance inverter in the carrier path.
• Without proper phase alignment, the impedance seen by the carrier will not follow the ideal trajectory, causing efficiency collapse and increased AM-AM distortion.
• This phase sensitivity extends to the input network, where an input splitter must deliver signals to both amplifiers with precise relative phase and amplitude weighting.

While load modulation dramatically improves back-off efficiency, it introduces a complex nonlinearity profile that must be corrected by Digital Pre-Distortion (DPD).

• The abrupt turn-on of the peaking amplifier creates a gain expansion region in the AM-AM characteristic, followed by compression at saturation.
• The changing impedance environment causes a signal-dependent AM-PM distortion as the carrier amplifier's phase response varies with the instantaneous load impedance.
• These nonlinearities are dynamic and exhibit memory effects due to the thermal and electrical time constants of the active devices.
• Effective DPD models for Doherty amplifiers must capture both the static nonlinearity from load modulation and the dynamic memory effects for adequate Adjacent Channel Leakage Ratio (ACLR) correction.

In an Asymmetric Doherty design, the peaking amplifier is intentionally sized larger than the carrier amplifier (e.g., 2:1 or 3:1 power ratio). This extends the high-efficiency back-off range beyond the standard 6 dB.

• A 2:1 asymmetric Doherty achieves peak efficiency at 9 dB back-off, suitable for signals with very high PAPR.
• The load modulation mechanism remains the same, but the impedance transformation ratio and current injection profile are scaled accordingly.
• This approach trades increased circuit complexity and die area for greater efficiency at deeper back-off levels, which is increasingly important for massive MIMO arrays where per-element power consumption is tightly constrained.

The passive output network that physically sums the RF power from the carrier and peaking paths while executing the impedance inversion critical to load modulation. Typically realized with a quarter-wave transmission line, the combiner presents a high impedance to the carrier at low power levels, maximizing voltage swing and efficiency. As the peaking amplifier injects current, the impedance seen by the carrier drops, maintaining saturation. The design must account for parasitic reactances and harmonic terminations to prevent efficiency nulls across the operating band.

A two-port network that transforms a load impedance ZL to its dual Z₀²/ZL. In a Doherty amplifier, this network is essential for the active load-pull effect. When the peaking amplifier is off, it presents a high impedance; the inverter transforms this to a low impedance, effectively isolating the peaking path. As peaking current rises, the inverter ensures the carrier sees a progressively lower impedance, enabling continuous high-efficiency operation from the back-off point to peak power.

The power-added efficiency (PAE) of an amplifier when operating at an average output power significantly below its saturated maximum. Modern communication signals with high peak-to-average power ratios (PAPR) force amplifiers to operate at 6-12 dB back-off. Load modulation specifically targets this region, maintaining high efficiency where conventional Class-AB amplifiers collapse. Key metrics include:

• 6 dB OBO: Typical target for Doherty designs
• PAE > 50%: Benchmark for GaN Doherty at back-off
• Drain efficiency: Often used interchangeably in back-off analysis

A Doherty architecture where the peaking amplifier has a larger transistor periphery and higher saturated power capability than the carrier. This asymmetry extends the high-efficiency back-off range beyond the conventional 6 dB point. A 2:1 peaking-to-carrier ratio, for example, enables efficient operation at 9-10 dB back-off, accommodating signals with extreme PAPR. The design introduces challenges in phase alignment and gain balancing, requiring careful input drive splitting and often asymmetric combiner networks.

The large-signal output reflection coefficient of a power amplifier measured under nominal RF drive conditions. Unlike small-signal S22, Hot S22 captures the nonlinear output impedance variation that occurs during actual operation. This parameter is critical for Doherty combiner design because the load modulation trajectory depends on the true large-signal impedance of both the carrier and peaking devices. Inaccurate Hot S22 characterization leads to suboptimal load modulation, efficiency degradation, and increased linearization burden.

The precise calibration of electrical path lengths at the input and output of the carrier and peaking branches to ensure constructive in-phase power combining. Mismatched phase causes the peaking current to arrive at the combiner with an incorrect phase relationship, corrupting the load modulation trajectory. This results in:

• Reduced gain at peak power
• Efficiency degradation across the back-off range
• Increased AM-PM distortion requiring more aggressive digital predistortion
• Typical alignment tolerance: < 5 degrees at the carrier frequency