Doherty Power Amplifier

The defining operational principle of the Doherty architecture. As input drive increases, the peaking amplifier (biased Class-C) begins conducting and injects current into the combining node. This current injection actively varies the load impedance presented to the carrier amplifier (biased Class-AB). At peak power, both amplifiers see their optimal impedance for maximum efficiency. At 6-10 dB output back-off, the carrier sees a modulated higher impedance, maintaining voltage swing near saturation and preserving high power-added efficiency (PAE) where conventional amplifiers suffer significant efficiency collapse.

In an asymmetric Doherty design, the peaking amplifier transistor has a larger periphery and higher saturated power capability than the carrier device. This extends the high-efficiency back-off range beyond the conventional 6 dB limit. Common ratios include 1:2 or 1:3 (carrier:peaking). The larger peaking device delivers proportionally more current during envelope peaks, enabling load modulation to occur deeper into back-off. This is critical for modern signals with peak-to-average power ratios (PAPR) exceeding 9 dB, such as 5G NR waveforms using OFDM with high-order QAM constellations.

The Doherty combiner relies on an impedance inverter, typically realized as a quarter-wave transmission line at the output of the carrier amplifier. This two-port network transforms the load impedance to its inverse value. When the peaking amplifier is off at low power, the inverter presents a high impedance to the carrier, maximizing voltage swing. As the peaking amplifier activates and injects current, the inverter transforms the decreasing impedance at the combining node into an increasing impedance at the carrier's drain, enabling the active load-pull effect fundamental to Doherty operation.

Precise phase alignment between the carrier and peaking branches is non-negotiable for proper Doherty operation. The electrical path lengths at both the input and output must be calibrated to ensure constructive in-phase power combining at the Doherty combiner output. Input phase offset networks compensate for the different bias-dependent phase shifts of Class-AB and Class-C amplifiers. Output phase alignment ensures the peaking amplifier's current injection arrives in phase at the combining node. Gain mismatch or phase misalignment degrades load modulation, collapses efficiency, and introduces severe AM-PM distortion that complicates digital predistortion linearization.

The Doherty architecture inherently embodies the linearity-efficiency trade-off. While load modulation dramatically improves back-off efficiency, the Class-C biasing of the peaking amplifier and the impedance transitions introduce significant nonlinearities. Key distortion mechanisms include:

• AM-AM distortion: Gain compression at the transition point where the peaking amplifier turns on
• AM-PM distortion: Phase discontinuities caused by the peaking amplifier's input capacitance variation with drive level
• Memory effects: Thermal and trapping time constants in GaN HEMT devices that cause dynamic distortion These nonlinearities necessitate digital predistortion to meet ACLR and EVM specifications while preserving the efficiency advantage.

Conventional Doherty designs are inherently narrowband due to the frequency-dependent behavior of the quarter-wave impedance inverter. Broadband Doherty architectures employ wideband impedance transformers and post-matching networks to extend operational bandwidth. In a post-matching Doherty, individual matching networks are placed after each transistor before the combiner, isolating device parasitics and simplifying the inverter design. These topologies maintain consistent load modulation and efficiency across extended continuous frequency ranges, critical for multi-band 5G base stations operating across disparate FR1 spectrum allocations.

The fundamental operating principle of the Doherty amplifier. It is a dynamic impedance transformation mechanism where the peaking amplifier's current injection actively varies the load impedance seen by the carrier amplifier. As the peaking device turns on during signal peaks, it pulls the load line of the carrier, allowing it to operate closer to saturation and maintain high efficiency over a wide Output Back-Off (OBO) range.

The primary amplifier stage, typically biased in Class-AB, that operates continuously. It handles signal amplification up to the transition point where the peaking amplifier activates. Its design is critical for low-level signal integrity and overall linearity. The carrier device's characteristics heavily influence the AM-AM Distortion and AM-PM Distortion profiles that Digital Pre-Distortion must later correct.

The auxiliary amplifier stage, typically biased in Class-C, that activates only during high signal envelope peaks. Its primary role is to supply additional current for load modulation. The peaking amplifier's turn-on characteristic is a major source of nonlinearity, creating a sharp discontinuity in the overall gain and phase response that sophisticated Neural Network Linearization models must capture.

The output network that combines the outputs of the carrier and peaking amplifiers. It incorporates an Impedance Inverter, often realized as a quarter-wave transformer, to perform the necessary impedance transformations for load modulation. The combiner's design, including its Harmonic Termination strategy, directly impacts bandwidth, efficiency, and the severity of Memory Effects.

A design variant where the peaking amplifier has a larger transistor periphery and higher saturated power capability than the carrier amplifier. This asymmetry extends the high-efficiency back-off range beyond the standard 6 dB, making it suitable for signals with very high Peak-to-Average Power Ratios (PAPR). The resulting Gain Mismatch requires careful Phase Alignment and places a greater burden on the linearization system.

Gallium Nitride High Electron Mobility Transistors are the dominant semiconductor technology for modern Doherty amplifiers. Their wide bandgap enables high power density, high operating voltage, and superior thermal characteristics. However, GaN devices exhibit complex Self-Heating Effects and Trap Effects, which introduce low-frequency dispersion and long-term Memory Effects that must be compensated by advanced Thermal Memory Effect Compensation algorithms.