Zero-Copy Buffer

In a traditional copy-based pipeline, each processing stage allocates new memory and executes a memcpy() to duplicate data. A zero-copy buffer bypasses this entirely by passing a pointer (a memory address reference) to the next stage. The underlying data remains in its original physical memory location, and ownership is transferred logically. This eliminates the CPU cycles spent on copying and the memory bandwidth consumed by redundant read/write operations, which is critical when processing high-bandwidth IQ streams at gigasamples per second.

Zero-copy is most effective when paired with a Direct Memory Access (DMA) engine. Instead of the CPU orchestrating data movement, the DMA controller transfers IQ samples directly from an ADC or FPGA into a pre-allocated memory region. The CPU then receives a pointer to that region without ever touching the data bus. This bus-mastering technique frees the processor for higher-value tasks like inference scheduling and decision logic, enabling true hardware-software co-design for minimal latency.

A common zero-copy implementation uses a lock-free ring buffer in shared memory. A producer (e.g., an FPGA offload engine) writes IQ samples into a circular buffer, advancing a write pointer. A consumer (e.g., an inference runtime) reads from a read pointer. Because both operate on the same physical memory, no copy occurs. Key design considerations include:

• Cache coherency management to prevent stale reads
• Memory ordering barriers to ensure correct visibility of writes
• Backpressure signaling when the buffer is full

Advanced zero-copy techniques leverage the Memory Management Unit (MMU) to remap virtual memory pages. Instead of copying data between user-space and kernel-space, the OS modifies page table entries so both contexts point to the same physical frames. Technologies like Linux's splice() and vmsplice() system calls, or mmap() with MAP_SHARED, enable this. For real-time RF systems, this avoids expensive context switches and data copies across the user-kernel boundary, preserving deterministic latency budgets.

On multi-socket systems with Non-Uniform Memory Access (NUMA) architecture, zero-copy requires careful memory placement. A buffer allocated on socket 0's memory controller will incur high access latency if the inference engine runs on socket 1. True zero-copy performance demands NUMA-aware allocation using APIs like libnuma or numactl to pin memory and threads to the same node. This ensures that pointer passing does not inadvertently introduce cross-socket bandwidth bottlenecks that negate the benefits of avoiding a copy.

For GPU-accelerated modulation classification, zero-copy refers to pinned (page-locked) host memory accessible directly by the GPU over PCIe via Direct Memory Access (DMA) . Using CUDA's cudaHostAlloc() with the cudaHostAllocMapped flag, the GPU kernel can read IQ samples from host memory without an explicit cudaMemcpy(). This overlaps data transfer with computation, critical for streaming inference where the latency of a synchronous copy would violate the inference latency budget.