Sample Rate Decimation

Decimation is not simply dropping samples; it is a two-stage process to prevent spectral corruption. The Nyquist-Shannon theorem dictates that the new sample rate must remain at least twice the highest frequency component of interest.

• Stage 1: Digital Anti-Aliasing Filter: A low-pass filter (often a Finite Impulse Response (FIR) or CIC filter) attenuates all frequency components above the new Nyquist limit.
• Stage 2: Downsampling: The filtered signal is then resampled by retaining only every M-th sample, where M is the decimation factor.
• Consequence of Failure: Skipping the filter step causes high-frequency noise and signals to fold back into the baseband spectrum, creating irreversible interference that confuses a downstream Automatic Modulation Classifier.

For large decimation factors, a multi-stage approach is computationally optimal. A single-stage FIR filter with a very sharp transition band requires an impractically long number of taps.

• Single-Stage: Simple to design but computationally prohibitive for large M. The filter order grows linearly with the decimation factor.
• Multi-Stage: Breaks the total decimation factor M into a product of smaller factors (M = M1 × M2 × ...). Each stage relaxes the filter requirements, drastically reducing the total multiply-accumulate operations (MACs) per second.
• Example: Decimating by 1000 is often done with a CIC filter (M=100) followed by a polyphase FIR filter (M=10), rather than a single, massive filter.

A polyphase decomposition is the most efficient way to implement a decimation FIR filter. It rearranges the filter's multiply-add operations to avoid computing output samples that will simply be discarded.

• Principle: The original FIR filter is partitioned into M parallel sub-filters (phases). The input commutator distributes samples to each phase, and the outputs are summed.
• Computational Savings: The filtering arithmetic is performed entirely at the low output sample rate, not the high input rate. This is a foundational block in GNU Radio decimating blocks and modern Digital Down Converters (DDCs).
• Benefit: This structure is inherently parallelizable, mapping perfectly to the DSP slices in modern FPGA offload architectures.

A Digital Down Converter (DDC) is the canonical implementation of decimation in an SDR system. It performs the complete translation of a digitized IF or RF signal to a complex baseband representation.

• Core Components: A Numerically Controlled Oscillator (NCO) for mixing, a CORDIC algorithm for complex rotation, and a multi-stage decimation filter chain.
• Function: The DDC selects a specific channel from a wideband spectrum and reduces its sample rate to a manageable level for a general-purpose processor or Edge TPU.
• Real-World Use: In a Real-Time Spectrum Classification system, a DDC extracts a 200 kHz narrowband signal from a 100 MHz wideband capture, decimating it to a 250 kSps IQ stream for inference.

A digital circuit that performs frequency translation, filtering, and decimation to convert a high-sample-rate digitized signal to a lower-rate complex baseband representation. The DDC is the primary hardware context where decimation occurs:

• Mixes the signal with a numerically controlled oscillator (NCO) to shift the band of interest to baseband
• Applies a low-pass filter to prevent aliasing before decimation
• Executes the decimation-by-M operation to reduce the sample rate
• Often implemented on FPGAs using CORDIC algorithms for efficient complex rotation

A computationally efficient structure that combines filtering and decimation into a single optimized operation. Instead of filtering then discarding samples, the polyphase decomposition rearranges the filter coefficients into M parallel sub-filters:

• Each sub-filter operates at the lower output rate, saving M-fold computational resources
• Commonly used to channelize a wideband signal into multiple narrowband sub-channels
• Enables parallel modulation classification across many frequency channels simultaneously
• Critical for real-time systems where a single wideband capture must feed multiple classifiers

A mandatory preprocessing step applied before any decimation operation to prevent spectral overlap and irreversible distortion. Without proper anti-aliasing, frequency components above the new Nyquist rate fold back into the passband:

• Typically implemented as a finite impulse response (FIR) or cascaded integrator-comb (CIC) filter
• Must attenuate all energy above Fs_new / 2 to below the noise floor
• The filter's transition band and stopband attenuation directly impact downstream classification accuracy
• In multi-stage decimation, each stage requires its own anti-aliasing filter with progressively relaxed specifications

The end-to-end data path that ingests raw In-phase and Quadrature samples from an RF receiver and delivers them to a classification model. Decimation is a critical rate-matching stage within this pipeline:

• Wideband capture at hundreds of MSPS must be reduced to match classifier input requirements (often 1-20 MSPS)
• Decimation bridges the gap between Direct RF Sampling frontends and narrowband processing backends
• Zero-copy buffer techniques pass decimated data between stages via pointer references
• Backpressure handling ensures the decimator does not overflow downstream inference engines

A multiplierless filter structure ideal for high-rate decimation in the first stage of a multi-stage decimation chain. CIC filters exploit recursive addition and subtraction to achieve large decimation factors with minimal hardware:

• Requires no multipliers, only adders and delay elements — perfect for FPGA implementation
• Effective for decimation factors of 8 to 8192 in a single stage
• Introduces a sinc-shaped passband droop that must be compensated by a subsequent FIR filter
• Commonly paired with a CIC compensation FIR and a final shaping filter in a complete DDC chain

The strategic selection of which Nyquist zone to sample and decimate from when using direct RF sampling. Decimation can be used to alias a signal from a higher Nyquist zone down to baseband intentionally:

• A signal in the 2nd Nyquist zone (Fs/2 to Fs) appears reversed in frequency after decimation
• Spectral inversion must be corrected digitally if the modulation classifier expects a specific orientation
• Multi-zone receivers use decimation chains to simultaneously extract signals from different Nyquist zones
• Understanding zone mapping is critical for correct modulation classification of high-frequency signals captured via undersampling