Glossary

Systolic Array

A homogeneous network of tightly coupled processing elements that rhythmically compute and pass data, providing a highly efficient hardware architecture for accelerating the matrix multiplications central to deep learning.

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HARDWARE ARCHITECTURE

What is a Systolic Array?

A systolic array is a homogeneous network of tightly coupled processing elements (PEs) that rhythmically compute and pass data, providing a highly efficient hardware architecture for accelerating the matrix multiplications central to deep learning.

A systolic array is a specialized hardware architecture consisting of a grid of identical processing elements (PEs) that operate in a lock-step, pipelined fashion. Data flows rhythmically through the array in a synchronized manner, analogous to the pumping of blood by the heart, with each PE performing a simple multiply-accumulate (MAC) operation and passing the result to its neighbor. This design eliminates costly memory accesses for intermediate results, maximizing data reuse and throughput for dense linear algebra.

In deep learning inference, systolic arrays excel at accelerating general matrix multiply (GEMM) operations, which form the computational backbone of convolutional and fully connected layers. By orchestrating the flow of input activations, weights, and partial sums across the PE grid, these arrays achieve high utilization of DSP slices on FPGAs or tensor cores on ASICs. The Google TPU is a canonical example, using a large 2D systolic array to deliver tera-scale operations per second for low-latency neural network execution.

SYSTOLIC ARRAY ANATOMY

Key Architectural Features

The defining characteristics that make systolic arrays the dominant compute fabric for deep learning acceleration, enabling deterministic dataflow and massive parallelism.

Rhythmic Dataflow Execution

Data pulses through the array in lockstep with a global clock, eliminating random memory access patterns. Each processing element (PE) receives data, performs a multiply-accumulate (MAC) operation, and passes results to its neighbor on the next cycle. This deterministic movement minimizes control overhead and maximizes throughput for matrix multiplication and convolution primitives.

2D Mesh Interconnect Topology

Processing elements are arranged in a grid with nearest-neighbor connections only. This spatial architecture avoids long global wires and fan-out bottlenecks. Data flows in multiple directions simultaneously:

Weight-stationary: Weights pre-loaded and held in each PE
Output-stationary: Partial sums accumulate locally
Row-stationary: Optimized for convolutional layers by reusing row data across filters

Multiply-Accumulate Primitive

Each PE contains a MAC unit that executes a = a + (b × c) in a single cycle. This operation is the atomic building block of linear algebra. Modern systolic arrays chain thousands of MACs together, achieving tera-operations per second (TOPS) throughput. The MAC directly maps to DSP48 slices in FPGAs and tensor cores in GPUs.

Pipeline Parallelism

Deep pipelines are inherent to the systolic design. As one wavefront of data propagates through the array, the next wavefront enters immediately behind it. This temporal parallelism keeps every PE busy on every clock cycle after the initial pipeline fill. Latency is determined by array dimensions, but throughput approaches one result per cycle.

Stationary Data Strategies

Different data reuse patterns optimize for specific workloads:

Weight Stationary: Minimizes weight movement for fully-connected layers; weights are pre-loaded into PEs
Input Stationary: Broadcasts activations across rows; ideal when batch size is large
Output Stationary: Accumulates partial sums locally; reduces read-write traffic to global buffers The choice directly impacts memory bandwidth utilization and energy efficiency.

Scalable Modular Design

Systolic arrays scale by tiling identical PE blocks. A 64×64 array can be composed of smaller sub-arrays, enabling designs from edge DPU accelerators to datacenter-scale TPU pods. This modularity allows designers to balance silicon area, power budget, and compute density for specific deployment targets.

COMPUTE FABRIC COMPARISON

Systolic Array vs. Other Compute Architectures

Architectural comparison of systolic arrays against alternative compute paradigms for accelerating the matrix multiplications central to deep learning inference.

Feature	Systolic Array	SIMD Vector	Spatial Dataflow
Data Movement Pattern	Rhythmic, nearest-neighbor only	Centralized register file to ALU	Producer-consumer FIFO channels
Memory Hierarchy Utilization	Minimal; data reused immediately upon arrival	Heavy reliance on multi-level caches	Scratchpad-based with explicit DMA
MAC Utilization Efficiency	90% sustained	60-80% (limited by cache misses)	85-95% (limited by routing congestion)
Control Overhead	Minimal; distributed SIMD-like control	Low; single instruction stream	Very low; fully decoupled kernels
Scalability	High; modular 2D tiling	Medium; limited by vector register width	Medium; limited by routing and place-and-route
Reconfigurability
Typical Target	TPU, custom ASIC, FPGA DPU	GPU, CPU SIMD extensions	FPGA, CGRA
Energy Efficiency (pJ/MAC)	0.1-0.5	1-10	0.5-2

Enabling Efficiency, Speed & Accuracy

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SYSTOLIC ARRAY ARCHITECTURE

Frequently Asked Questions

Explore the fundamental concepts behind systolic arrays, the rhythmic compute fabrics that power modern AI accelerators and real-time signal processing.

A systolic array is a homogeneous network of tightly coupled processing elements (PEs) that rhythmically compute and pass data in a synchronized, pipeline fashion—much like the rhythmic contraction of the human heart. Each PE performs a simple multiply-accumulate (MAC) operation on incoming data and forwards the result to its neighbor on the next clock cycle. Data flows through the array in a predetermined, regular pattern, typically from memory into the array edges and then systematically through the grid. The key architectural principle is that every data element is reused multiple times once fetched from memory, dramatically reducing the memory bandwidth bottleneck. For example, in a weight-stationary systolic array used for matrix multiplication, weights are pre-loaded into the PEs, input activations flow left-to-right, and partial sums flow top-to-bottom, accumulating the final dot-product results at the bottom edge. This deterministic dataflow eliminates global synchronization overhead and enables extremely high throughput with minimal control logic, making systolic arrays the computational backbone of Google's TPU and numerous custom AI accelerators.

SYSTOLIC ARRAY ECOSYSTEM

Related Terms

Core architectural concepts and optimization techniques that interact with systolic arrays to accelerate deep learning inference on FPGAs and custom silicon.

Multiply-Accumulate (MAC)

The fundamental arithmetic operation executed by each processing element within a systolic array. A MAC operation consists of a multiplication of two operands followed by an addition of the product to an accumulator: a ← a + (b × c). In FPGA fabric, MAC operations map directly to DSP48 slices, which are hardened silicon blocks optimized for high-speed digital signal processing. The computational throughput of a systolic array is typically measured in MACs per second or TOPS (Tera Operations Per Second). For modulation classification workloads, efficient MAC utilization directly determines the real-time inference capacity for streaming IQ samples.

DSP48

FPGA Primitive

a+(b×c)

Core Operation

Deep Learning Processor Unit (DPU)

A programmable inference engine designed by Xilinx/AMD that is built around a configurable systolic array architecture. The DPU features a custom instruction set optimized specifically for convolutional neural network operations, including convolution, pooling, and element-wise activation functions. Key architectural components include:

A systolic array of MAC units for matrix multiplication
On-chip buffer memory to minimize external DRAM access
A dedicated data dispatcher that orchestrates dataflow between memory and compute DPUs are the primary deployment target for Vitis AI compiled models and are widely used for real-time RF signal classification on Zynq and Versal platforms.

EXPLORE

Operator Fusion

A graph-level optimization that combines multiple consecutive neural network operations into a single computational kernel executed on the systolic array. By fusing operations such as convolution + batch normalization + ReLU, intermediate data transfers to off-chip memory are eliminated. Benefits include:

Reduced memory bandwidth bottlenecks
Lower kernel launch overhead
Improved data locality within the systolic array pipeline For FPGA-based modulation classifiers, operator fusion is critical for achieving the sub-millisecond latency required by real-time spectrum monitoring applications. The Vitis AI compiler performs this optimization automatically during model compilation.

3-in-1

Typical Fusion Depth

Streaming Architecture

An FPGA dataflow design pattern where IQ samples are processed as a continuous sequence through a deeply pipelined systolic array without waiting for complete frames. This architecture achieves minimal processing latency because computation begins as soon as the first data element arrives. Key characteristics:

Line-buffer based processing for convolutional layers
Ping-pong buffering to overlap data transfer with computation
Deterministic latency suitable for hard real-time constraints Streaming architectures are the preferred deployment pattern for real-time automatic modulation classification where every microsecond of processing delay impacts spectrum responsiveness.

< 1 µs

Per-Sample Latency

Data Packing

A hardware optimization technique that concatenates multiple low-precision data elements into a single wide memory word before feeding them into the systolic array. For example, eight INT8 weights can be packed into a single 64-bit bus transfer. This maximizes the utilization of:

Memory bandwidth between DRAM and on-chip buffers
SIMD vector units within the processing elements
The internal data width of the systolic array's interconnect When combined with post-training quantization to INT8 precision, data packing enables systolic arrays to achieve 4x higher effective throughput compared to FP32 processing for modulation classification inference.

Throughput Gain with INT8

Roof-line Model

A visual performance analysis tool that plots computational throughput (operations/second) against operational intensity (operations/byte) to identify performance bottlenecks in systolic array designs. The model reveals whether a specific neural network workload is:

Compute-bound: Limited by the peak MAC throughput of the systolic array
Memory-bound: Limited by the DRAM bandwidth feeding data to the array The 'roof' is defined by the hardware's peak compute capacity and maximum memory bandwidth. For FPGA-based modulation classifiers, the roof-line model guides hardware-aware architecture selection, helping engineers balance DSP slice allocation against memory interface configuration for optimal inference performance.

Ops/Byte

Key Metric

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.

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