Roof-line Model

The roof-line model divides performance into two distinct regimes separated by the ridge point:

• Memory-Bound (Left of Ridge): The workload's operational intensity is low. Performance is limited by how fast data can be fetched from off-chip DRAM. Optimizations should focus on reducing memory traffic through operator fusion, data packing, and quantization.
• Compute-Bound (Right of Ridge): The workload has sufficient data reuse to saturate memory bandwidth. Performance is limited by the peak floating-point or integer throughput of DSP slices and logic fabric. Optimizations target increased parallelism and pipelining.

The ridge point itself represents the minimum operational intensity required to achieve peak compute performance on a specific hardware platform.

Operational intensity is the ratio of total arithmetic operations to total bytes of data movement, measured in FLOPs/Byte or OPs/Byte:

• Formula: Operational Intensity = Total Operations / Total DRAM Bytes Transferred
• For a convolutional layer processing IQ samples, operations include all multiply-accumulate (MAC) computations across filters and input channels.
• Data movement includes reading input feature maps, filter weights, and writing output activations.
• Higher operational intensity indicates better data reuse. Techniques like depthwise separable convolution and batch normalization folding directly alter this ratio by reducing either operations or memory traffic.
• The x-axis of the roof-line plot represents this metric on a logarithmic scale.

The roof-line itself is defined by two hardware-imposed ceilings:

• Peak Memory Bandwidth (Sloped Roof): The maximum rate at which the FPGA's memory controller can transfer data from DRAM to the processing fabric. This creates a linear slope where Attainable Performance = Operational Intensity × Peak Bandwidth.
• Peak Compute Throughput (Flat Roof): The maximum number of operations the FPGA can execute per second, determined by the total available DSP slices, LUT-based multipliers, and clock frequency. This creates a horizontal ceiling.
• The actual performance of a modulation classifier kernel cannot exceed either bound.
• Integer-only inference and custom systolic array designs can raise the compute ceiling by maximizing DSP utilization per clock cycle.

Model compression techniques directly shift a workload's position on the roof-line plot:

• Post-Training Quantization (PTQ) from FP32 to INT8 reduces data movement by 4×, increasing operational intensity and potentially moving a memory-bound classifier closer to the ridge point.
• Weight pruning removes redundant MAC operations, shifting the workload leftward on the x-axis but also reducing total operations on the y-axis. The net effect depends on whether the sparsity pattern enables reduced memory traffic.
• Operator fusion combines convolution, bias, and activation layers into a single kernel, eliminating intermediate memory transactions and increasing effective operational intensity.
• Hardware-aware NAS can search for architectures that sit precisely at the ridge point, achieving optimal balance between compute utilization and bandwidth efficiency for a specific FPGA target.

Beyond moving a workload along the roof-line, engineers can raise the ceilings themselves through hardware-level optimizations:

• Data packing concatenates multiple INT8 or INT4 values into a single wide memory word (e.g., 512-bit AXI interface), effectively multiplying the usable bandwidth without changing the physical DRAM interface.
• Ping-pong buffering with on-chip BRAM decouples data transfer from computation, hiding memory latency and allowing the compute fabric to operate closer to peak throughput.
• Streaming architectures process IQ samples as a continuous pipeline, eliminating the need for large off-chip buffers and reducing overall DRAM traffic.
• In-memory computing approaches bypass the von Neumann bottleneck entirely by performing MAC operations within the memory array, fundamentally altering the roof-line shape for analog compute fabrics.

A complete modulation classification pipeline—from IQ preprocessing to final softmax—consists of multiple kernels with different operational intensities:

• Each layer or fused kernel occupies a distinct point on the roof-line plot. A bottleneck analysis identifies which kernel is furthest from its respective ceiling.
• Early convolutional layers processing raw IQ samples typically have high operational intensity due to weight reuse across spatial dimensions, often landing in the compute-bound regime.
• Fully connected classification heads have low operational intensity (few operations per weight byte), frequently falling in the memory-bound regime.
• Mixed-precision quantization assigns higher bit-widths to compute-bound layers and aggressive low-bit quantization to memory-bound layers, optimizing the entire pipeline holistically.
• Tools like Vitis AI and hls4ml provide per-layer roof-line visualizations to guide this layer-wise optimization strategy.