Static Power vs. Dynamic Power

Static power is the constant power dissipated by a digital circuit when it is powered on but not actively switching. It is caused by subthreshold leakage current flowing through transistors even when they are nominally 'off'. This power is independent of clock speed or computational activity. Key factors influencing static power include:

• Process Technology: Smaller transistor geometries (e.g., 28nm vs. 180nm) exhibit exponentially higher leakage.
• Supply Voltage (Vdd): Static power has a super-linear relationship with Vdd.
• Temperature: Leakage current increases dramatically with junction temperature.
• Standard Cell Libraries: Use of high-Vt (threshold voltage) cells reduces leakage at the cost of slower switching speeds. For a typical microcontroller in a sleep state, static power can range from microamps to milliamps, dominating total energy consumption in long idle periods.

Dynamic power is the power consumed during active computation due to the charging and discharging of capacitive loads (wires and transistor gates) during logic transitions. It is the primary power cost of performing inference. The classic equation is P_dynamic = α * C * V² * f, where:

• α (Activity Factor): The probability a gate will switch in a clock cycle (typically 0.1-0.2 for neural network layers).
• C (Load Capacitance): The total capacitive load being switched.
• V (Supply Voltage): The core voltage, which has a quadratic impact.
• f (Clock Frequency): The switching rate. In TinyML, dynamic power spikes during the execution of compute-intensive layers like convolutions. Techniques like clock gating and dynamic voltage and frequency scaling (DVFS) directly target dynamic power reduction.

The physical origins of static and dynamic power are distinct and rooted in semiconductor physics.

Static Power Sources:

• Subthreshold Leakage: Current flowing between source and drain when the transistor is in weak inversion.
• Gate Oxide Tunneling: Current leaking through the thin insulating gate oxide.
• Reverse-Bias Junction Leakage: Minority carrier diffusion in reverse-biased p-n junctions.

Dynamic Power Sources:

• Capacitive Switching Energy: The dominant component, required to charge the gate capacitance of fan-out transistors and wire capacitance to logic '1' and discharge it to '0'.
• Short-Circuit (Crowbar) Current: A brief period during switching when both PMOS and NMOS transistors are partially on, creating a direct path from Vdd to GND. Understanding these causes informs low-level optimization, such as choosing a semiconductor process node or implementing power gating to eliminate leakage in idle blocks.

The proportion of static vs. dynamic power varies drastically based on the system's operational state, which is central to TinyML duty-cycling strategies.

Active Inference Mode:

• Dynamic power dominates. The processor cores, memory, and accelerators are clocked, performing millions of switches per second.
• Power draw can be 10-1000x higher than in sleep mode.

Deep Sleep / Standby Mode:

• Static power dominates. Clocks are halted, and most logic is power-gated or in a retention state.
• Only essential always-on domain circuits (e.g., a real-time clock or wake-up controller) leak current.

Key TinyML Strategy: Minimize the product of active power and inference time, then maximize the length of deep sleep periods where only static power is paid. This is quantified by the energy per inference metric.

Design choices at the model and hardware level directly determine the balance and magnitude of power consumption.

Model Architecture Impact:

• Dynamic Power: Models with higher MACC counts and activation sparsity directly influence the activity factor (α). Quantized models (e.g., INT8 vs. FP32) reduce the switched capacitance (C) in arithmetic units.
• Static Power: Larger models with more parameters require more SRAM for weights, increasing the total silicon area and thus aggregate leakage current.

Hardware Architecture Impact:

• Dynamic Power: Dedicated neural processing unit (NPU) accelerators with optimized dataflows achieve the same computation with far fewer memory accesses, reducing dynamic energy.
• Static Power: Systems-on-Chip with fine-grained power gating can shut off leakage in unused NPU tiles, SRAM banks, or peripherals. The choice of process corner (fast vs. low-power) trades off dynamic performance for static leakage.

Accurately attributing power consumption requires specialized measurement methodologies.

Direct Measurement:

• Using a high-precision digital multimeter or source measurement unit (SMU) in series with the power supply to sample current at a high rate (kHz+).
• Calculating Energy: Integrating the current-voltage product over the exact inference window: E_inference = ∫ V(t) * I(t) dt.

On-Chip Estimation:

• Performance Counters: Some MCUs provide counters for clock cycles, cache misses, etc., which can be correlated with power models.
• Internal Current Sensors: Advanced microcontrollers integrate on-die current sensors for coarse-grained monitoring.

Profiling Workflow:

1. Measure total system power in deep sleep to establish static power baseline.
2. Execute a single inference in a tight loop, measuring total active power.
3. The difference is the dynamic power contribution for that workload.
4. Use layer-wise profiling tools to attribute dynamic power to specific network layers. Tools like the MLPerf Tiny Profiler or vendor-specific suites assist in this analysis.

Energy per inference is the total electrical energy, measured in microjoules (µJ) or millijoules (mJ), consumed to complete a single forward pass of a machine learning model. It is the definitive metric for battery life calculation in TinyML.

• Calculation: Integrates both static and dynamic power over the exact inference time: Energy = (Static Power + Dynamic Power) × Inference Latency.
• Primary Use: Enables direct comparison of model efficiency across different hardware platforms, independent of clock speed.
• Example: A keyword spotting model consuming 150 µJ per inference on an Arm Cortex-M4 allows for precise battery runtime projections.

Inference latency is the time delay from input presentation to prediction output. It directly determines the duration of high dynamic power consumption.

• Critical Relationship: Dynamic power is only consumed during active computation. Therefore, reducing latency directly reduces the dynamic energy component.
• Trade-off: Optimizations like quantization reduce latency (and dynamic energy) but may increase static power if they require more memory accesses or complex control logic.
• Measurement: Typically measured in milliseconds (ms) for microcontroller targets. Profiling tools break this down into per-layer timings.

Power-aware TinyML encompasses design techniques that minimize and manage total energy consumption, explicitly targeting both static and dynamic power domains.

• Static Power Reduction: Techniques include power gating unused peripherals or memory banks, and selecting microcontrollers with low-leakage process technology.
• Dynamic Power Reduction: Techniques include model compression (pruning, quantization), voltage scaling, and adaptive frequency scaling based on workload.
• System Design: Involves duty cycling, where the device sleeps (near-zero static power) between inference bursts, making average power a function of wake-up interval and inference energy.

Thermal throttling is a hardware protection mechanism where a processor reduces its clock speed or voltage to lower power dissipation and prevent overheating.

• Direct Impact on Power: Dynamic Power ∝ C × V² × f. Throttling reduces frequency (f) and often voltage (V), causing a super-linear drop in dynamic power.
• TinyML Relevance: While more common in larger SoCs, dense microcontroller deployments or continuous high-throughput inference can cause heat buildup, triggering throttling and increasing inference latency.
• Design Implication: Power and thermal profiles must be co-analyzed to ensure sustained performance without violating junction temperature limits.

Worst-Case Execution Time is the maximum possible time an inference task could take under all permissible operating conditions, including worst-case data paths and cache states.

• Power Analysis Link: WCET is used to calculate worst-case energy consumption, which is critical for safety-critical and real-time systems. Formula: Worst-Case Energy = (Static Power × WCET) + Dynamic Energy(WCET).
• Determinism: Achieving deterministic WCET often requires disabling features like caches that improve average-case performance but add timing variability, impacting the dynamic power profile.
• Use Case: Essential for designing reliable battery-operated systems that must guarantee a minimum operational lifetime under all conditions.

Hardware-in-the-Loop testing is a validation methodology where the actual target microcontroller executes the model within a controlled test environment that simulates real-world inputs and measures outputs.

• Power Measurement: HIL setups integrate precision ammeters or sense resistors with data acquisition systems to measure current draw at high sampling rates, enabling precise separation of static and dynamic power.
• Profile Generation: Captures real, non-simulated power traces that account for all silicon characteristics, PCB effects, and firmware overhead.
• Golden Standard: Provides the most accurate data for energy-per-inference and power profiling, validating estimates from datasheets or software simulators.